AX88850 ASIX [ASIX Electronics Corporation], AX88850 Datasheet - Page 24

• Manufacturer Part Number: AX88850
• Description: 100BASE-TX/FX Repeater Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

3.11 LED Interface
AX88850 provides per-port LED status indication for partition, jabber, link/activity and support rate-based LED for
global utilization (%) and global collision frequency (%). Detail function is described on previous pin description
(LED interface). LED[7:0] are all active low.
3.11.1 LED Status Driver wave-form for AX88851
Note 1 :
Note 2 : Reference port map as following table (Using per port Carrier Sense / Receive Signal Detect to identify port
LED_SYN
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
a.
b.
c.
d.
e.
f.
g.
AX88851
AX88852
AX88853
AX88854
number).
P17~0 indicates partition status for each port
J17~0 indicates jabber status for each port
L17~0 indicates link status for each port
A17~0 indicates activity status for each port
RID4~0 is the ID number of repeater chip
The LED display support two estimations:C4~0 and CC4~0 which indicate global collision rate for
each 104.8ms sampling period. Users can choose any one presentation.
The LED display support two estimations:U4~0 and UU4~0 which indicate global utilization rate for
each 104.8ms sampling period. Users can choose any one presentation.
AX88850
P 0
P 1
P 2
P 3
P 4
P 5
P 6
P 7
D 0
J 0
J 1
J 2
J 3
J 4
J 5
J 6
J 7
Port[7:0] == M0_CRS[7:0]
Port[3:0] == M0_CRS[3:0]
Port[7:0] == RSD[7:0]
Reference to AX88851/AX88853 depended on MEDIA setting.
D 1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
D 2
C 4
U 4
J 8
J 9
A 8
A 9
P 8
P 9
D 3
C 2
C 3
U 0
U 1
U 2
U 3
C 0
C 1
P10
P11
P12
P13
P14
P15
P16
P17
D 4
J10
J11
J12
J13
J14
J15
J16
J17
D 5
A10
A11
A12
A13
A14
A15
A16
A17
Port[9:8] == CRS[1:0]
Port[9:8] == CRS[1:0]
Port[9:8] == CRS[1:0]
D 6
RID0
RID1
RID2
RID3
RID4
C C 4
U U 4
24
"0"
D 7
C C 0
C C 1
C C 2
C C 3
U U 0
U U 1
U U 2
U U 3
D 8
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
ASIX ELECTRONICS CORPORATION
D 9 D10 ~ D15
Port[17:10] == M1_CRS[7:0]
Port[7:4] == M1_CRS[3:0]
PRELIMINARY
P 0
P 1
P 2
P 3
P 4
P 5
P 6
P 7
D 0
J 0
J 1
J 2
J 3
J 4
J 5
J 6
J 7
D 1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
D 2
C 4
U 4
J 8
J 9
A 8
A 9
P 8
P 9
D 3