K9K8G08U0M Samsung, K9K8G08U0M Datasheet - Page 9

• Manufacturer Part Number: K9K8G08U0M
• Description: 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory
• Manufacturer: Samsung

Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
Caution :
Product Introduction
The K9K8G08U0M is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-
dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made
up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists
of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program
and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-
sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0M.
The K9K8G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space
requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9K8G08U0M.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
The K9WAG08U1M is composed of two K9K8G08U0M chips which are selected separately by each CE1 and CE2. Therefore, in
terms of each CE, the basic operation of K9WAG08U1M is same with K9K8G08U0M except some AC/DC charateristics.
K9WAG08U1M
K9K8G08U0M
Read
Read for Copy Back
Read ID
Reset
Page Program
Two-Plane Page Program
Copy-Back Program
Two-Plane Copy-Back Program
Block Erase
Two-Plane Block Erase
Random Data Input
Random Data Output
Read Status
Read EDC Status
Chip1 Status
Chip2 Status
2. Read EDC Status is only available on Copy Back operation.
3. Interleave-operation between two chips is allowed.
4. Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .
It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.
Any undefined command inputs are prohibited except for above command set of Table 1.
Function
(3)
(3)
(2)
(1)
(1)
(4)
(4)
1st Cycle
80h---11h
85h---11h
60h---60h
FFh
7Bh
F1h
F2h
00h
00h
90h
80h
85h
60h
85h
05h
70h
9
2nd Cycle
81h---10h
81h---10h
D0h
D0h
30h
35h
10h
10h
E0h
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O
O
O
O
Preliminary