DM9161CI DAVICOM [Davicom Semiconductor, Inc.], DM9161CI Datasheet - Page 31

• Manufacturer Part Number: DM9161CI
• Description: Industrial-Temperature 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
33
17.8-17.4 PHYADR[4
17.3-17.0 ANMB[3:0]
17.11-
17.15
17.14
17.13
17.12
17.9
Bit
Bit Name
Reserved
100HDX
100FDX
10HDX
10FDX
:0]
(PHYADR),
Default
1, RO
1, RO
1, RO
1, RO
0, RO
0, RO
RW
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after auto-
negotiation. This bit is invalid when it is not in the auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after auto-
negotiation. This bit is invalid when it is not in the auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after auto-
negotiation. This bit is invalid when it is not in the auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after auto-
negotiation. This bit is invalid when it is not in the auto-negotiation mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written
to these bits.
b3
0
0
0
0
0
0
0
0
1
b2 b1 B0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
Description
Version: DM9161CI-DS-F01
DM9161CI
February 22, 2012
Final