IS75V16F128GS32-7065BI ISSI [Integrated Silicon Solution, Inc], IS75V16F128GS32-7065BI Datasheet
IS75V16F128GS32-7065BI
Related parts for IS75V16F128GS32-7065BI
IS75V16F128GS32-7065BI Summary of contents
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... IS75V16F128GS32 3.0 Volt Multi-Chip Package (MCP) — 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM MCP FEATURES • Power supply voltage 2.7V to 3.3V • High performance: Flash: 70ns maximum access time PSRAM: 65ns maximum access time • Package: 107-ball BGA • ...
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... IS75V16F128GS32 GENERAL DESCRIPTION This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM. Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152 words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable, Output Enable, and A0-A20 are shared among the three memories ...
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... IS75V16F128GS32 PIN CONFIGURATION (128 Mb Flash and 32 Mb PSRAM) PACKAGE CODE: B 107 BALL FBGA (Top View) (9. 10.00 mm Body, 0.8 mm Ball Pitch GND GND H NC CEf1 OE J CE1r ...
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... IS75V16F128GS32 DEVICE BUS OPERATION CE2r OE (1,2) OPERATION Full Standby Output Disable ( (4) Read from FLASH Read from FLASH 2 ...
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... IS75V16F128GS32 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Tstg Storage Temperature T Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins IN OUT ( Supply ( Supply CC CC RESET1, RESET2 V IN WP/ACC (4) V ACC Notes: 1. Voltage is defined on the basis of GND = 0 V. ...
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... IS75V16F128GS32 DC CHARACTERISTICS Symbol Parameter I Input Leakage LI I Output Leakage LO RESET Inputs I LIT Leakage Current I 1f FLASH Vcc (1) CC Active Current (Read FLASH Vcc Active (2) CC Current(Program/Erase) OE FLASH Vcc Active (5) CC Current (Read-While-Program) ( FLASH Vcc Active CC Current (Read-While-Erase ...
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... IS75V16F128GS32 DC CHARACTERISTICS (Continued) Symbol Parameter I r PSRAM V Power Down Current (8) (8M Partial) V Input Low Level IL V Input High Level (FLASH 1 or FLASH Input High Level (PSRAM Voltage for Sector Protection ID and Temp. Unprotection(RESET) Voltage for WP/ACC V ACC Sector Protection/Unprotection ...
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... IS75V16F128GS32 AC CHARACTERISTICS - TIMING CE CE Parameter CEf Recover Time CEf Hold Time CE1r High to WE Invalid time for Standby Entry TIMING DIAGRAM FOR ALTERNATING PSRAM TO CEf CE1r WE CE2r 8 Symbol Condition t — CCR t — CHOLD t — CHWX FLASH CCR t CHOLD t CHWX ...
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... IS75V16F128GS32 FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2 Sector Bank Address K-Word Bank A SA0 4 Bank A SA1 4 Bank A SA2 4 Bank A SA3 4 Bank A SA4 4 Bank A SA5 4 Bank A SA6 4 Bank A SA7 4 Bank A SA8 32 Bank A SA9 32 Bank A SA10 32 Bank A SA11 32 Bank A SA12 32 Bank A SA13 32 Bank A SA14 ...
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... IS75V16F128GS32 FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2 Sector Bank Address K-Word Bank C SA72 32 Bank C SA73 32 Bank C SA74 32 Bank C SA75 32 Bank C SA76 32 Bank C SA77 32 Bank C SA78 32 Bank C SA79 32 Bank C SA80 32 Bank C SA81 32 Bank C SA82 32 Bank C SA83 32 Bank C SA84 32 Bank C SA85 32 Bank C SA86 ...
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... IS75V16F128GS32 USER CONFIGURABLE BANK ARCHITECTURE TABLE - FLASH 1 or FLASH 2 Virtual Bank 1 Bank Split Volume Choice 1 8 Mbit Choice 2 24 Mbit Choice 3 24 Mbit Choice 4 8 Mbit EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE - FLASH 1 or FLASH 2 Virtual Bank 1 Bank Split Volume Combination Choice 1 ...
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... IS75V16F128GS32 SIMULTANEOUS OPERATION TABLE - FLASH 1 or FLASH 2 Case Note writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C, and Bank D ...
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... IS75V16F128GS32 SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 Bank Address Bank Sector A 21 Bank A SA0 0 Bank A SA1 0 Bank A SA2 0 Bank A SA3 0 Bank A SA4 0 Bank A SA5 0 Bank A SA6 0 Bank A SA7 0 Bank A SA8 0 Bank A SA9 0 Bank A SA10 0 Bank A SA11 0 Bank A SA12 0 Bank A SA13 0 Bank A ...
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... IS75V16F128GS32 SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 Bank Address Bank Sector A 21 Bank B SA33 0 Bank B SA34 0 Bank B SA35 0 Bank B SA36 0 Bank B SA37 0 Bank B SA38 0 Bank B SA39 0 Bank B SA40 0 Bank B SA41 0 Bank B SA42 0 Bank B SA43 0 Bank B SA44 0 Bank B SA45 0 Bank B SA46 0 Bank B ...
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... IS75V16F128GS32 SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 Bank Address Bank Sector A 21 Bank B SA66 0 Bank B SA67 0 Bank B SA68 0 Bank B SA69 0 Bank B SA70 0 Bank C SA71 1 Bank C SA72 1 Bank C SA73 1 Bank C SA74 1 Bank C SA75 1 Bank C SA76 1 Bank C SA77 1 Bank C SA78 1 Bank C SA79 1 Bank C ...
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... IS75V16F128GS32 SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 Bank Address Bank Sector A 21 Bank C SA100 1 Bank C SA101 1 Bank C SA102 1 Bank C SA103 1 Bank C SA104 1 Bank C SA105 1 Bank C SA106 1 Bank C SA107 1 Bank C SA108 1 Bank C SA109 1 Bank C SA110 1 Bank C SA111 1 Bank C SA112 1 Bank C SA113 1 Bank C ...
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... IS75V16F128GS32 SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 Sector SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 ...
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... IS75V16F128GS32 SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 Sector SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 ...
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... IS75V16F128GS32 FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2 Bus First Bus Command Cycle Write Sequence Cycle Req'd Addr. 1 (1) XXXh Read / Reset (1) Read / Reset 3 555h Autoselect 3 555h 4 555h Program 1 BA Program Suspend BA 1 Program Resume 6 Chip Erase 555h 6 555h Sector Erase ...
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... IS75V16F128GS32 FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2 Notes: • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA). • Bus operations are defined in "DEVICE BUS OPERATIONS” ...
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... IS75V16F128GS32 FLASH READ ONLY OPERATIONS CHARACTERISTICS - FLASH 1 or FLASH 2 Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First ...
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... IS75V16F128GS32 FLASH READ CYCLE - FLASH 1 or FLASH 2 Address CEf1 OE WE High Address Stable t ACC OEH t CE Integrated Silicon Solution, Inc. — www.issi.com — ISSI High-Z Output valid 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00D 03/24/03 ® ...
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... IS75V16F128GS32 RESET RESET / READ OPERATION TIMING DIAGRAM - FLASH 1 or FLASH 2 RESET FLASH HARDWARE RESET RESET Address CEf1 RESET High-Z DQ Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00D 03/24/ Address Stable t ACC 1-800-379-4774 ISSI t OH Output valid ® ...
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... IS75V16F128GS32 FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2 Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from High During Toggle Bit Polling Data Setup Time Data Hold Time ...
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... IS75V16F128GS32 FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2 Parameter OE Setup Time to WE Active (2) CE Setup Time to WE Active (2) f Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-Out Time ...
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... IS75V16F128GS32 FLASH WRITE CYCLE - FLASH 1 or FLASH 2 (WE CONTROL) 3rd Bus Cycle 555h ADDRESS t WC CEf GHWL WE DQ Notes address of the memory location to be programmed data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. ...
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... IS75V16F128GS32 FLASH WRITE CYCLE - FLASH 1 or FLASH 2 (CEf CONTROL) 3rd Bus Cycle 555h ADDRESS CEf1 GHEL WE DQ Notes address of the memory location to be programmed data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. ...
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... IS75V16F128GS32 FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS - FLASH 1 or FLASH 2 ADDRESS CEf1 GHWL VCS Vccf Notes the sector address for Sector Erase. Address = 555h for Chip Erase 555h 2AAh 555h WPH ...
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... IS75V16F128GS32 FLASH AC WAVEFORMS FOR DATA DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2 CEf1 Data / Data In t RY/BY Notes: DQ7 = Valid Data (the device has completed the Embedded operation Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00D ...
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... IS75V16F128GS32 FLASH AC WAVEFORMS FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2 ADDRESS CEf1 WE t OEH /DQ Data BUSY RY/BY Notes: 1 DQ6 stops toggling (the device has completed the Embedded operation AHT ASO AHT AS t CEPH t OEPH ...
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... IS75V16F128GS32 FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM - FLASH 1 or FLASH 2 Read t RC BA1 ADDRESS CEf1 OE t GHWL WE Valid DQ Output Note: 1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Virtual Bank 1. BA2: Address of Virtual Bank 2. Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS75V16F128GS32 TIMING DIAGRAM FLASH RY/BY DURING WRITE/ERASE OPERATIONS - FLASH 1 or FLASH 2 CEf WE RY/BY FLASH RESET, RESET, RESET, RESET, RY/BY RESET TIMING DIAGRAM - FLASH 1 or FLASH RESET RY/BY 32 The rising edge of the last write pulse Entire programming or erase operations t BUSY READY Integrated Silicon Solution, Inc. — ...
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... IS75V16F128GS32 FLASH TEMPORARY SECTOR GROUP UNPROTECTION - FLASH 1 or FLASH 2 t VCCf VIDR t VCS VID 3V RESET CEf1 WE RY/BY Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00D 03/24/03 t VLHT Program or Erase Command Sequence Unprotection Period 1-800-379-4774 ISSI ® t VLHT t VLHT 33 ...
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... IS75V16F128GS32 FLASH ACCELERATED PROGRAM - FLASH 1 or FLASH 2 VCCf t VCS VACC VIH WP/ACC CEf1 WE RY/ VACCR t VLHT Program Command Sequence Acceleration Period Integrated Silicon Solution, Inc. — www.issi.com — ISSI ® t VLHT t VLHT 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00D 03/24/03 ...
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... IS75V16F128GS32 FLASH EXTENDED SECTOR GROUP PROTECTION- FLASH 1 or FLASH 2 t VCS Vccf t VLHT RESET t VIDR Address A6 CEf1 OE WE Data Notes: 1 SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected, . TIME-OUT: Time-Out window Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS75V16F128GS32 FLASH ERASE AND PROGRAMMING PERFORMANCE - FLASH 1 or FLASH 2 Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Note: 1. Typical Erase conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Typical Program conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Data= Checker 36 Min. ...
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... IS75V16F128GS32 PSRAM POWER DOWN PROGRAM KEY TABLE Basic KEY Table Definition A16 KEY Mode Select Available KEY Table A16 MODE Mode Select NAP Partial H SLEEP H Notes: 1: The Power Down Program can be performed one time after compliance of Power-up timings and it should not be re-programmed after regular Read or Write ...
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... IS75V16F128GS32 PSRAM READ OPERATIONS Parameter Read Cycle Time (1,3) Chip Enable Access Time (1) Output Enable Access Time (1,4) Address Access Time (1) Output Data Hold Time CE1r Low to Output Low-Z (2) OE Low to Output Low-Z (2) CE1r High to Output High-Z (2) OE High to Output High-Z (2) Address Setup Time to CE1r Low ...
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... IS75V16F128GS32 PSRAM WRITE OPERATIONS Parameter Write Cycle Time (1) Address Setup Time (2) (2) Address Hold Time CE1r Write Setup Time CE1r Write Hold Time WE Setup Time WE Hold Time LB adnd UB Setup Time LB adnd UB Hold Time OE Setup Time (3) OE Hold Time (3,4) OE Hold Time (5) OE High to CE1r Low Setup Time ...
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... IS75V16F128GS32 PSRAM POWER DOWN PARAMETERS Parameter CE2r Low Setup Time for Power down Entry CE2r Low Hold Time after Power down Entry CE1r High Hold Time Following CE2r High after Power down Exit SLEEP Mode only CE1r High Setup Time following CE2r High after Power down Exit ...
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... IS75V16F128GS32 PSRAM READ TIMING (OE Control Access) ADDRESS CE1r (Output) Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low. PSRAM READ TIMING (CE1r Control Access) ADDRESS t ASC CE1r OE t BSC ...
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... IS75V16F128GS32 (Address Access after OE Control Access) PSRAM READ TIMING ADDRESS (A20-A3) ADDRESS (A2-A0) CE1r (Output) Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low. (Address Access after CE1r Control Access) ...
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... IS75V16F128GS32 PSRAM WRITE TIMING (CE1r Control) Address t AS CE1r UB OHCL OE DQ (Input) Note: CE2r and PE must be High during write cycle. PSRAM WRITE TIMING (WE Control, Single Write Operation) Address CE1r WE UB (Input) Note: CE2r and PE must be High during write cycle. ...
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... IS75V16F128GS32 PSRAM WRITE TIMING (WE Control, Continuous Write Operation) ADDRESS CE1r WE UB (Input) Note: CE2r and PE must be High during write cycle. PSRAM READ / WRITE TIMING ADDRESS t CE1r WE t CHBH UB Read Data Output Note: Write address is valid from either CE1r last falling edge. ...
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... IS75V16F128GS32 PSRAM READ / WRITE TIMING ADDRESS CE1r WE UB Write Data Input Note: The t is specified from the time satisfied oth t OEH PSRAM READ / WRITE TIMING ADDRESS Low CE1r WE UB Read Data Output Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE. Integrated Silicon Solution, Inc. — ...
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... IS75V16F128GS32 PSRAM READ / WRITE TIMING Address CE1r Low WE UB Write Data Input Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled OE. 46 (READ = OE Control, WRITE = WE Control Read Address t ASO t t OEH ...
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... IS75V16F128GS32 PSRAM POWER DOWN TIMING CE1r PE ADDRESS A20-A16 Note: CE2r must be High for Power Down Programming. Any other inputs not specified above can be either High or Low. PSRAM STANDBY ENTRY and EXIT TIMING CE1r CE2r DQ Power Down Entry Note: This Power Down mode can be also used for Power-up Timing #2 except that t Power-up Timing. Integrated Silicon Solution, Inc. — ...
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... IS75V16F128GS32 PSRAM POWER UP TIMING 1 CE1r CE2r Note: The C2LH specifies after Vccr reaches specfied minimum level. PSRAM POWER UP TIMING 2 CE1r CE2r Vccr 0 V C2HL specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must t Note: The be brought to High prior to or together with CE2r Low to High transition ...
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... IS75V16F128GS32 PSRAM DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V Vccr Data Retention Supply Voltage DR I Vccr Data Retention Supply Current Vccr Data Retention Supply Current DR t Data Retention SetupTime DRS t Data Retention RecoveryTime DRR Voltage Transition Time CCR Note ...
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... IS75V16F128GS32 PIN CAPACITANCE Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C 2 Control Pin Capacitance IN Notes: 1. Test conditions T = +25 ° 1.0 MHz A HANDLING OF PACKAGE: Please handle this package carefully because the sides of the package have acute angles. CAUTION: 1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET. 2) Without the high voltage (VID) sector group protection can be achieved by using the “ ...
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... IS75V16F128GS32 MINI BALL GRID ARRAY – 107-Ball BGA PACKAGE CODE: B (9. 10.00 mm Body, 0.8 mm Ball Pitch SEATING PLANE Symbol Min. Typ. A 1.15 1.25 A1 0.05 0.10 D 9.90 10.00 D1 — 8.80 E 8.90 9.00 E1 — 7.20 e — 0.80 Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS75V16F128GS32 ORDERING INFORMATION o Industrial Range: - +85 Flash Bank Order Part No. Organization IS75V16F128GS32-7065BI User Configurable Flash Speed(ns) 70 Integrated Silicon Solution, Inc. — www.issi.com — ISSI PSRAM Speed(ns) Package 65 107-ball BGA 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00D ® 03/24/03 ...