S9S12P96J0VFTR Freescale Semiconductor, S9S12P96J0VFTR Datasheet - Page 65

• Manufacturer Part Number: S9S12P96J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P96J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 6 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C

1. Read: Always reads 0x00
1. Read: Anytime. The data source is depending on the data direction value.
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
2.3.7
2.3.8
Freescale Semiconductor
Function
Address 0x0004 to 0x0007
Address 0x0008
6-5, 3-2
Write: Unimplemented
Write: Anytime
pin values.
Altern.
Field
Reset
Reset
PE
PE
7
W
W
R
R
Port E general purpose input/output data—Data Register, ECLKX2 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port E general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
ECLKX2
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
PIM Reserved Register
Port E Data Register (PORTE)
PE7
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PE6
—
0
0
0
6
6
Table 2-8. PORTE Register Field Descriptions
Figure 2-6. Port E Data Register (PORTE)
S12P-Family Reference Manual, Rev. 1.13
Figure 2-5. PIM Reserved Register
PE5
—
5
0
0
5
0
ECLK
PE4
0
0
0
4
4
Description
PE3
—
0
0
0
3
3
PE2
—
0
0
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
—
PE1
IRQ
0
0
1
1
(2)
Access: User read
XIRQ
PE0
—
0
0
0
0
2
65
(1)
(1)