LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 347
LPC1113FHN33/203,5
Manufacturer Part Number
LPC1113FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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Table 306. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
UM10398
User manual
Bit
0
1
2
3
Symbol
EM0
EM1
EM2
EM3
0x4001 003C) bit description
19.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)
19.7.9 Capture Register (CT16B0CR0/1 - address 0x4000 C02C/30 and
Value
CT16B1CR0/1 - address 0x4001 002C/30)
Each Capture register is associated with a device pin and may be loaded with the
counter/timer value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 305: Capture registers (TMR16B0CR0/1, address 0x4000 C02C/30 and TMR16B1CR0/1,
The External Match Register provides both control and status of the external match
channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0].
If the match outputs are configured as PWM output in the PWMCON registers
(Section
rules
Bit
15:0
31:16
Description
External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6]
control the functionality of this output. This bit is driven to the
CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output match channel 2, whether or not
this output is connected to its pin. When a match occurs between the TC and MR2, this
bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output. Note that on counter/timer 0 this match channel is not pinned
out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the
IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output of match channel 3. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin
available for this channel on either of the 16-bit timers.
(Section 19.7.13 “Rules for single edge controlled PWM outputs” on page
19.7.12), the function of the external match registers is determined by the PWM
Symbol
CAP
-
address 0x4001 002C/30) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
Description
Timer counter capture value.
Reserved.
UM10398
© NXP B.V. 2012. All rights reserved.
351).
347 of 538
Reset
value
0
-
Reset
value
0
0
0
0
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