C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 359
C8051F962-A-GM
Manufacturer Part Number
C8051F962-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F962-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
DQFN-76
Mounting Style
SMD/SMT
Number Of Programmable I/os
57
Number Of Timers
4
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SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1
SFR Page = 0x0 and 0xF; SFR Address = 0xE2
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
Name
Reset
Type
2:0
Bit
Bit
7
6
5
4
3
PCA0ME PCA0 Module I/O Enable.
Unused
SPI1E
Name
ECIE
R/W
T1E
T0E
7
0
Read = 0b; Write = Don’t Care.
SPI0 I/O Enable.
0: SPI1 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P2.0.
Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
PCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
SPI1E
MISO (for SPI1) routed to P2.1.
MOSI (for SPI1) routed to P2.2.
NSS (for SPI1) routed to P2.3 only if SPI1 is configured to 4-wire mode.
R/W
6
0
R/W
T1E
5
0
T0E
R/W
Rev. 0.5
4
0
Function
ECIE
R/W
3
0
2
0
PCA0ME[2:0]
C8051F96x
R/W
1
0
0
0
359
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