XRT91L82ES Exar, XRT91L82ES Datasheet - Page 45

• Manufacturer Part Number: XRT91L82ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L82ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
REV. P1.0.5
xr
xr
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
TXSCLKOOFF Transmit Serial Clock Output Tristate
CDRLCKREF
DISRDCLK
Reserved
Reserved
Reserved
Reserved
DISRD
N
AME
T
ABLE
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
Receive Parallel Data Output Disable
If this bit is set to "0", the 16-bit parallel receive data output will
asynchronously mute.
"0" = Forces RXDO[15:0]P/N to a logic state "0"
"1" = Normal Mode
Receive Parallel Clock Output Disable
This bit is used to asynchronously control the activity of the parallel
receive clock output.
"0" = Forces RXPCLKOP/N to a logic state of "0"
"1" = Normal Mode
This bit is used to control the activity of the 2.488/2.666 GHz
differential serial clock output. Tristating TXSCLKOP/N output
reduces power consumption.
"0" = TXSCLKOP/N output Enabled
"1" = TXSCLKOP/N output Tristated
CDR’s Recovered High-speed Serial Clock Reference
Controls CDR’s operation.
"0" = Forced to lock to CDR PLL reference training clock
"1" = Normal Operation (Locked to incoming serial data)
18: M
ICROPROCESSOR
O
UTPUT
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
C
ONTROL
F
UNCTION
R
42
EGISTER
R
EGISTER
0
X
(0
04
X
04
H
H
B
)
IT
D
ESCRIPTION
Register
Type
R/W
R/W
R/W
R/W
X
X
X
X
XRT91L82
(HW reset)
Default
Value
X
X
X
X
1
1
1
1