1893Y-10LFT IDT, 1893Y-10LFT Datasheet - Page 117

• Manufacturer Part Number: 1893Y-10LFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893Y-10LFT

• Rohs: yes
• Part # Aliases: ICS1893Y-10LFT

ICS1893 Rev C 6/6/00
Table 9-6.
RXCLK
MII Pin
Name
ICS1893 - Release
SRCLK
MAC/Repeater Interface Pins: 100M Symbol Interface (Continued)
Symbol
Name
100M
Pin
No.
Pin
38
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Output
Type
Pin
(Symbol) Receive Clock.
In Symbol Mode, the ICS1893 sources an SRCLK to a
MAC/repeater. The SRCLK synchronizes the signals on the
SRD[4:0] pins between the ICS1893 and the MAC/repeater.
The following table contrasts the SRCLK behavior when the
mode for the ICS1893 is either 10Base-T or 100Base-TX.
Note: The signal on the SRCLK pin is conditioned by the
The SRCLK frequency is
2.5 MHz.
The ICS1893 generates its
SRCLK from the MDI data
stream using a digital PLL.
When the MDI data stream
terminates the PLL
continues to operate,
synchronously referenced
to the last packet received.
The ICS1893 switches
between clock sources
during the period between
when its SCRS is asserted
and prior to its RXDV being
asserted. While the
ICS1893 is locking onto
the incoming data stream,
a clock phase change of
up to 360 degrees can
occur.
The RXCLK aligns once
per packet.
117
RXTRI pin.
10Base-T
Chapter 9 Pin Diagram, Listings, and Descriptions
Pin Description
The SRCLK frequency is
25 MHz.
The ICS1893 generates its
SRCLK from the MDI data
stream while there is a
valid link (that is, either
data or IDLEs). In the
absence of a link, the
ICS1893 uses the REF_IN
clock to generate the
SRCLK.
While the ICS1893 is
bringing up a link, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once,
when the link is being
established.
100Base-TX
June, 2000