1893Y-10LFT IDT, 1893Y-10LFT Datasheet - Page 26

• Manufacturer Part Number: 1893Y-10LFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893Y-10LFT

• Rohs: yes
• Part # Aliases: ICS1893Y-10LFT

6.1 MII Data Interface
ICS1893 Rev C 6/6/00
The most common configuration for an ICS1893’ s MAC/Repeater Interface is the Medium Independent
Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893 MAC/Repeater Interface is
configured for the MII Data Interface mode, data is transferred between the PHY and the MAC/repeater as
framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to
synchronize the transfers.
The ICS1893 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit
and a receive data path to synchronously exchange 4 bits of data (that is, nibbles).
•
•
Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by
the ICS1893 (that is, the ICS1893 sources the TXCLK and RXCLK signals to the MAC/repeater).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICs1893 is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
•
•
As mentioned in
it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1893 isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit pins
(TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1893
enables its MII and enables its Twisted-Pair Transmit signals.
The ICS1893’ s MII transmit data path includes the following:
The ICS1893’ s MII receive data path includes the following:
Half-duplex mode, the ICS1893 asserts the Carrier Sense signal when data is being either transmitted or
received. While operating in half-duplex mode, the ICS1893 also asserts its Collision Detect signal to
indicate that data is being received while a transmission is in progress.
Full-duplex mode, the ICS1893 asserts the Carrier Sense signal only when receiving data and forces the
Collision Detect signal to remain inactive.
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
ICS1893 Data Sheet - Release
Section 5.1.1.3, “ Hot Insertion”
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
, the ICS1893 design allows hot insertion of its MII. That is,
26
Chapter 6 Interface Overviews
June, 2000