1893Y-10LFT IDT, 1893Y-10LFT Datasheet - Page 20

• Manufacturer Part Number: 1893Y-10LFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893Y-10LFT

• Rohs: yes
• Part # Aliases: ICS1893Y-10LFT

5.1 Reset Operations
5.1.1 General Reset Operations
5.1.1.1
5.1.1.2
5.1.1.3
ICS1893 Rev C 6/6/00
This section first discusses reset operations in general and then specific ways in which the ICS1893 can be
configured for various reset options.
The following reset operations apply to all the specific ways in which the ICS1893 can be reset, which are
discussed in
When the ICS1893 enters a reset condition (either through hardware, power-on reset, or software), it does
the following:
1. Isolates the MAC/Repeater Interface input pins
2. Drives all MAC/Repeater Interface output pins low
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
4. Initializes all its internal modules and state machines to their default states
5. Enters the power-down state
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
When the ICS1893 exits a reset condition, it does the following:
1. Exits the power-down state
2. Latches the Serial Management Port Address of the ICS1893 into the Extended Control Register, bits
3. Enables all its internal modules and state machines
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
As with the ICS189X products, the ICS1893 reset design supports ‘ hot insertion’ of its MII. (That is, the
ICS1893 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the
MAC/repeater.)
Entering Reset
Exiting Reset
Hot Insertion
Register bits to their default values
16.10:6. [See
associated ICS1893 input pins, as determined by the HW/SW pin
(TXCLK) and receive clock (RXCLK)
is removed
ICS1893 Data Sheet - Release
Section 5.1.2, “ Specific Reset Operations”
Section 8.11.3, “ PHY Address (bits 16.10:6)”
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
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Chapter 5 Operating Modes Overview
June, 2000