S9S08DZ60F2MLH Freescale Semiconductor, S9S08DZ60F2MLH Datasheet - Page 148

• Manufacturer Part Number: S9S08DZ60F2MLH
• Description: 8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
• Manufacturer: Freescale Semiconductor

Specifications of S9S08DZ60F2MLH

• Rohs: yes
• Core: HCS08
• Processor Series: MC9S08DZ60
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 60 KB
• Data Ram Size: 4 K
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
In FLL bypassed internal mode, the MCGOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL clock frequency locks to 1024 times the
reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL
is disabled in a low power state.
8.4.1.4
In FLL bypassed external (FBE) mode, the MCGOUT clock is derived from the external reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the external reference clock.
The FLL bypassed external mode is entered when all the following conditions occur:
In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency
locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from
the FLL and the PLL is disabled in a low power state.
8.4.1.5
The PLL engaged external (PEE) mode is entered when all the following conditions occur:
In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source The PLL clock frequency locks to a
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LP bit is written to 0
CLKS bits are written to 10
IREFS bit is written to 0
PLLS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
LP bit is written to 0
CLKS bits are written to 00
IREFS bit is written to 0
PLLS bit is written to 1
RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
FLL Bypassed External (FBE)
PLL Engaged External (PEE)
It is possible to briefly operate in FBE mode with an FLL reference clock
frequency that is greater than the specified maximum frequency. This can be
necessary in applications that operate in PEE mode using an external crystal
with a frequency above 5 MHz. Please see
from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz
for a detailed example.
MC9S08DZ60 Series Data Sheet, Rev. 4
NOTE
8.5.2.4, “Example # 4: Moving
Freescale Semiconductor