S9S08DZ60F2MLH Freescale Semiconductor, S9S08DZ60F2MLH Datasheet - Page 209

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S9S08DZ60F2MLH

Manufacturer Part Number
S9S08DZ60F2MLH
Description
8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S08DZ60F2MLH

Rohs
yes
Core
HCS08
Processor Series
MC9S08DZ60
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
60 KB
Data Ram Size
4 K
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT

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11.4
This section provides a complete functional description of the IIC module.
11.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication
is described briefly in the following sections and illustrated in
Freescale Semiconductor
AD[10:8]
GCAEN
ADEXT
Field
2–0
7
6
Start signal
Slave address transmission
Data transfer
Stop signal
Functional Description
IIC Protocol
General Call Address Enable. The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled
Address Extension. The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
scheme. This field is only valid when the ADEXT bit is set.
Table 11-8. IICC2 Field Descriptions
MC9S08DZ60 Series Data Sheet, Rev. 4
Description
Figure
Chapter 11 Inter-Integrated Circuit (S08IICV2)
11-9.
209

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