74LVC1G08GW-Q100 NXP Semiconductors, 74LVC1G08GW-Q100 Datasheet
74LVC1G08GW-Q100
Specifications of 74LVC1G08GW-Q100
Related parts for 74LVC1G08GW-Q100
74LVC1G08GW-Q100 Summary of contents
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Single 2-input AND gate Rev. 1 — 9 July 2012 1. General description The 74LVC1G08-Q100 provides one 2-input AND function. Inputs can be driven from either 3 devices. This feature allows the use of these ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC1G08GW-Q100 40 C to +125 C 40 C to +125 C 74LVC1G08GV-Q100 4. Marking Table 2. Marking Type number 74LVC1G08GW-Q100 74LVC1G08GV-Q100 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off OFF CC leakage current I supply current GND 1. 5 I additional per pin supply current input V = 3.3 V ...
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... NXP Semiconductors 12. AC waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. The input output Y propagation delays Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 6. Test circuit for measuring switching times Table 10 ...
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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...
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... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions) UNIT 0.100 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT753 Fig 8. Package outline SOT753 (SC-74A) 74LVC1G08_Q100 Product data sheet scale ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G08_Q100 v.1 20120709 74LVC1G08_Q100 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline ...