DS32512W Maxim Integrated, DS32512W Datasheet - Page 12

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

5.5 Bit Error-Rate Tester (BERT) Features
5.6 Clock Adapter
5.7 Parallel Microprocessor Interface Features
5.8 SPI Serial Microprocessor Interface Features
5.9 Miscellaneous Features
5.10 Test Features
5.11 Loopback Features
One BERT per port
Software programmable for insertion toward the transmit line interface or the receive system interface
Generates and detects pseudo-random patterns of length 2
32 bits in length
Large 24-bit error counter and 32-bit bit counter allows testing to proceed for long periods without host
intervention
Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
Pattern synchronization even in the presence of 10
Creates DS3, E3, STS-1, and/or telecom bus clocks from single input reference clock
Input reference clock can be DS3, E3, STS-1, 12.8MHz, 19.44MHz, 38.88MHz, or 77.76MHz
Use of common system timing frequencies such as 19.44MHz eliminates the need for any local oscillators,
reducing cost and board space
Very small jitter gain and intrinsic jitter generation
Derived clocks can be output for external system use
Transmit signals using CLAD clocks meet Telcordia (DS3) and ITU (E3) jitter and wander requirements
Multiplexed or nonmultiplexed 8- or 16-bit interface
Configurable for Intel mode (CS, WR, RD) or Motorola mode (CS, DS, R/W)
Ready (
Operation up to 10Mbps
Burst mode for multibyte read and write accesses
Programmable clock polarity and phase
Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
Global reset input pin
Global interrupt output pin
Two programmable I/O pins per port
Five pin JTAG port
All functional pins are in-out pins in JTAG mode
Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
HIZ
TEST
Analog local loopback—ALB (transmit line output to receive line input)
Diagnostic local loopback—DLB (transmit framer interface to receive framer interface)
Line loopback—LLB (receive clock and data recover to transmit waveshaping)
Optional AIS generation on the line side of the loopback during diagnostic loopback
pin to force all digital output and I/O pins into a high-impedance state
pin for manufacturing test modes
RDY/ACK
) handshake output signal
12 of 130
-3
bit-error rate
n
- 1 (n = 1 to 32) and repetitive patterns from 1 to
DS32506/DS32508/DS32512