DS32512W Maxim Integrated, DS32512W Datasheet - Page 36

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

Figure 8-7. Jitter Attenuation/Jitter Transfer
8.5 BERT
Each LIU port has a built-in bit error-rate tester (BERT). The BERT is a software-programmable test-pattern
generator and monitor capable of meeting most error performance requirements for digital transmission equipment.
It can generate and synchronize to pseudo-random patterns with a generation polynomial of the form x
(where n and y can take on values from 1 to 32 with y < n) and to repetitive patterns of any length up to 32 bits.
The pattern generator generates the programmable test pattern, and inserts the test pattern into the data stream.
The pattern detector extracts the test pattern from the receive data stream and monitors it.
location of the BERT Block within the DS325xx devices.
8.5.1 Configuration and Monitoring
The pattern detector is always enabled. The pattern generator is enabled by setting the PORT.CR3:BERTE
configuration bit. When the BERT is enabled and PORT.CR3:BERTD=0, the pattern is transmitted and received in
the line direction, i.e. the pattern generator is the data source for the transmitter, and the receiver is the data source
for the pattern detector. When the BERT is enabled and PORT.CR3:BERTD=1, the pattern is transmitted and
received in the system direction, i.e. the pattern generator is the data source for the
pins, and the
The I/O of the BERT are binary (NRZ) format. Thus while the BERT is enabled, both PORT.CR2:RBIN and
PORT.CR2:TBIN must be set to 1 for proper operation. In addition, while transmitting/receiving BERT patterns in
the system direction (PORT.CR3:BERTD = 1), the neighboring framer or mapper component must also be
configured for binary interface mode to match the LIU. If the LIU interface is normally bipolar, the interface can be
changed back to bipolar mode when the system is done using the BERT function (PORT.CR3:BERTE = 0).
The following tables show how to configure the BERT to send and receive common patterns.
TPOS/TDAT
-10
-20
-30
25.2 Hz (STS -1)
21.7 Hz (DS3)
16.7 Hz (E3)
0
ATTENUATION
ATTENUATOR
DS3/E3/STS-1
10
WITH JITTER
ENABLED
MINIMUM
DS325xx
and
JITTER
27Hz
TNEG
40Hz
DS3 [GR - 253 (1999)]
CATEGORY I
100
pins are the data source for the pattern detector. See
1k
1k
FREQUENCY (Hz)
36 of 130
DS3 [GR - 499 (1995)]
CATEGORY I
STS- 1 [GR - 253 (1999)]
E3 [TBR24 (1997)]
CATEGORY II
10k
DS3 [GR - 499 (1999)]
40k 59.6k
CATEGORY II
100k
>150k
RPOS/RDAT
DS32506/DS32508/DS32512
DS325xx TYPICAL
RECEIVER JITTER
TRANSFER WITH
JITTER ATTENUATOR
DISABLED
1M
Figure
Figure 2-1
and
2-1.
RNEG/RLCV
n
shows the
+ x
y
+ 1,