DS32512W Maxim Integrated, DS32512W Datasheet - Page 2

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

1.
2.
3.
4.
5.
6.
7.
8.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10 T
5.11 L
7.1
7.2
8.1
8.2
8.3
8.4
8.5
STANDARDS COMPLIANCE .............................................................................................6
BLOCK DIAGRAM ..............................................................................................................7
APPLICATION EXAMPLE ..................................................................................................8
DETAILED DESCRIPTION..................................................................................................9
DETAILED FEATURES.....................................................................................................11
CONTROL INTERFACE MODES......................................................................................13
PIN DESCRIPTIONS .........................................................................................................14
FUNCTIONAL DESCRIPTION ..........................................................................................24
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Power-Down........................................................................................................................................ 26
8.2.11 Jitter Generation (Intrinsic).................................................................................................................. 26
8.2.12 Jitter Transfer ...................................................................................................................................... 26
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 Jitter Transfer ...................................................................................................................................... 35
G
R
T
J
B
C
P
SPI S
M
S
D
LIU M
T
R
J
BERT...........................................................................................................................................36
ITTER
ITTER
OOPBACK
RANSMITTER
EST
RANSMITTER
IT
ARALLEL
HORT
ECEIVER
LOCK
ETAILED
ECEIVER
LOBAL
ISCELLANEOUS
E
Transmit Clock .................................................................................................................................... 24
Framer Interface Format and the B3ZS/HDB3 Encoder..................................................................... 24
Error Insertion ..................................................................................................................................... 24
AIS Generation.................................................................................................................................... 25
Waveshaping ...................................................................................................................................... 25
Line Build-Out ..................................................................................................................................... 25
Line Driver........................................................................................................................................... 25
Interfacing to the Line ......................................................................................................................... 25
Driver Monitor and Output Failure Detection ...................................................................................... 26
Interfacing to the Line ......................................................................................................................... 30
Optional Preamp ................................................................................................................................. 30
Automatic Gain Control (AGC) and Adaptive Equalizer ..................................................................... 30
Clock and Data Recovery (CDR) ........................................................................................................ 31
Loss-of-Signal (LOS) Detector............................................................................................................ 31
Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 32
Power-Down........................................................................................................................................ 33
Input Failure Detection........................................................................................................................ 33
Jitter and Wander Tolerance............................................................................................................... 34
RROR
F
ERIAL
ODE
EATURES
A
A
A
P
F
TTENUATOR
TTENUATOR
DAPTER
IN
EATURES
P
.....................................................................................................................................11
.....................................................................................................................................30
M
-R
....................................................................................................................................24
F
D
IN
M
ICROPROCESSOR
EATURES
ESCRIPTIONS
ATE
ICROPROCESSOR
...............................................................................................................................11
D
...............................................................................................................................24
ESCRIPTIONS
............................................................................................................................12
...........................................................................................................................12
F
T
EATURES
ESTER
.......................................................................................................................11
.....................................................................................................................11
.....................................................................................................................35
...................................................................................................................12
(BERT) F
............................................................................................................14
..........................................................................................................12
........................................................................................................17
I
TABLE OF CONTENTS
NTERFACE
I
NTERFACE
EATURES
F
2 of 130
EATURES
F
EATURES
...............................................................................12
.....................................................................12
..................................................................12
DS32506/DS32508/DS32512