DS32512W Maxim Integrated, DS32512W Datasheet - Page 94

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

Table 11-3. Framer Interface Timing
(VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T
and
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
RCLK/TCLK Clock Period
RCLK Duty Cycle
TCLK Duty Cycle
LIU Reference Clock Duty Cycle
TPOS/TDAT, TNEG to TCLK Setup Time
TPOS/TDAT, TNEG Hold Time
RCLK to RPOS/RDAT, RNEG/RLCV
Value Change
RCLK Rise and Fall Time
TCLK Rise and Fall Time
Figure
DS3 mode.
78MHz is the maximum instantaneous frequency for a gapped clock. The maximum average frequency is 45.094MHz for DS3,
34.643MHz for E3, and 52.255MHz for STS-1.
E3 mode.
STS-1 mode.
Outputs loaded with 25pF, measured at 50% threshold.
Not tested during production test.
The LIU reference clock must be a
When TCLKI = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCLKI = 1, TPOS/TDAT and TNEG are
sampled on the falling edge of TCLK.
When RCLKI = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCLKI = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Outputs loaded with 25pF, measured between V
Measured between V
11-2.)
PARAMETER
IL(MAX)
and V
IH(MIN)
±
20ppm low-jitter clock. See Section
.
SYMBOL
t2/t, t3/t1
t2/t, t3/t1
t2/t, t3/t1
OL(MAX)
t1
t4
t5
t6
t7
t8
94 of 130
and V
(Notes 1, 2)
(Notes 2, 3)
(Notes 2, 4)
(Notes 5, 6)
(Note 6)
(Notes 6, 7)
(Notes 6, 8)
(Notes 6, 8)
(Notes 5, 6, 9)
(Notes 6, 10 )
(Notes 5, 11)
OH(MIN)
CONDITIONS
.
8.7.1
A
= -40°C to +85°C.) (See
for more information on reference clocks.
MIN
45
30
30
3
1
1
DS32506/DS32508/DS32512
TYP
22.4
29.1
19.3
50
1
Figure 11-1
MAX
55
70
70
7
2
2
UNITS
ns
ns
ns
ns
ns
ns
%
%
%