DS32512W Maxim Integrated, DS32512W Datasheet - Page 20

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

JAD[1:0]
JAS[1:0]
LBn[1:0]
RMONn
RLOSn
NAME
RCLKI
RBIN
ITRE
RPD
LBS
TYPE
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
O
I
Internal Termination Resistance Enable (Tx and Rx) (All Ports). This bit indicates when the
internal termination is enabled. See Section 8.2.8.
0 = Disabled. The transmitters and receivers are terminated externally.
1 = Enabled. The transmitters and receivers are terminated internally.
Receive Binary Interface Control (All Ports). See Section 8.3.6.
0 = Receiver framer interface is bipolar on the
encoder is disabled.
1 = Receiver framer interface is binary on the
enabled.
Receive Clock Invert Control (All Ports). See Section 8.3.6.3.
0 = RPOS/
1 = RPOS/
Receive Loss-of-Signal Status (Port n). This pin is asserted upon detection of 192
consecutive zeros in the receive data stream. It is deasserted when there are no excessive
zero occurrences over a span of 192 clock periods. An excessive zero occurrence is defined as
three or more consecutive zeros in DS3 and STS-1 modes or four or more zeros in E3 mode.
See Section 8.3.5.
Receive Monitor Preamp Control (Port n). This pin determines whether or not the receiver
preamp is enabled in port n to provide flat gain to the incoming signal before the AGC/equalizer
block processes it. This feature should be enabled when the device is being used to monitor
signals that have been resistively attenuated by a monitor jack. See Section
information.
0 = Disable the monitor preamp
1 = Enable the monitor preamp
Receive Power-Down (All Ports). See Section 8.3.7.
0 = Enable all receivers
1 = Power down all receivers
RNEGn/RLCVn
Jitter Attenuator Depth (All Ports). These pins are ignored when a microprocessor interface
is enabled
00 = 16 bits
01 = 32 bits
10 = 64 bits
11 = 128 bits
Jitter Attenuator Select (All Ports). These pins select the location of the jitter attenuator.
These pins are ignored when a microprocessor interface is enabled
8.4.
00 = Disabled
01 = Receive path
1X = Transmit path
Loopback Control (Port n). When only the hardware interface is enabled
HW
00 = No loopback
01 = Diagnostic loopback (DLB)
10 = Line loopback (LLB)
11 =
11 =
Loopback Select (All Ports). This pin specifies how the device interprets the
This pin is ignored when a microprocessor interface is enabled
= 1), these pins set the loopback mode for port n. See Section
(LBS
(LBS
= 0) Line loopback (LLB) and diagnostic loopback (DLB) simultaneously
= 1) Analog loopback (ALB)
RDAT
RDAT
(IFSEL
high impedance.)
and
and
≠ 000). See Section 8.4.
RNEG/RLCV
RNEG/RLCV
(RXPn/RXNn
20 of 130
update on the falling edge of RCLK.
update on the rising edge of RCLK.
FUNCTION
high impedance. RCLKn, RPOSn/RDATn, and
RDAT
RPOS
pin, and the B3ZS/HDB3 encoder is
and
RNEG
(IFSEL
DS32506/DS32508/DS32512
pins, and the B3ZS/HDB3
8.6.
(IFSEL
≠ 000). See Section 8.6.
(IFSEL
≠ 000). See Section
8.3.2
LBn[1:0]
for more
= 000 and
bits.