DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 218

• Manufacturer Part Number: DS26528GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GA4

• Part # Aliases: 90-26528-GA4

9.5
Table 9-14. LIU Register Set
Note: Reserved registers should only be written with all zeros.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Jitter Attenuator Depth Select (JADS).
Bits 3 and 2: Jitter Attenuator Position Select 1 and 0 (JAPS[1:0]). These bits are used to select the position of
the jitter attenuator.
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
Bit 0: LOS Criteria Selection (LCS). This bit is used for LIU LOS selection criteria.
1008h–101Fh
JAPS1
ADDRESS
0
0
1
1
1000h
1001h
1002h
1003h
1004h
1005h
1006h
1007h
LIU Register Definitions
0 = Jitter attenuator FIFO depth set to 128 bits.
1 = Jitter attenuator FIFO depth set to 32 bits. Use for delay-sensitive applications.
0 = E1
1 = T1 or J1
E1 Mode:
0 = G.775
1 = ETS 300 233
T1/J1 Mode:
0 = T1.231
1 = T1.231
JAPS0
—
7
0
0
1
0
1
LRISMR
LTITSR
LTRCR
LSIMR
NAME
LMCR
LRSR
LLSR
LRSL
—
Jitter attenuator is in the receive path.
Jitter attenuator is in the transmit path.
Jitter attenuator is not used.
Jitter attenuator is not used.
LTRCR
LIU Transmit Receive Control Register
1000h + (20h x n): where n = 0 to 7, for Ports 1 to 8
—
6
0
LIU Transmit Receive Control Register
LIU Transmit Impedance and Pulse Shape Selection Register
LIU Maintenance Control Register
LIU Real Status Register
LIU Status Interrupt Mask Register
LIU Latched Status Register
LIU Receive Signal Level Register
LIU Receive Impedance and Sensitivity Monitor Register
Reserved
FUNCTION
—
5
0
218 of 276
JADS
4
0
DESCRIPTION
JAPS1
3
0
DS26528 Octal T1/E1/J1 Transceiver
JAPS0
2
0
T1J1E1S
1
0
LSC
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R