DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 39

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

DS32506/DS32508/DS32512
Figure 8-9. Repetitive Pattern Synchronization State Diagram
Sync
1 bit error
Verify
Match
Pattern Matches
8.5.2.3
Receive Pattern Monitoring
Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts
the incoming bits. An Out Of Synchronization (BERT.SR:OOS = 1) condition is declared when the synchronization
state machine is not in the “Sync” state. An OOS condition is terminated when the synchronization state machine is
in the “Sync” state. A change of state of the OOS status bit sets the BERT.SRL:OOSL latched status bit and can
cause an interrupt if enabled by BERT.SRIE:OOSIE.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If the
two bits do not match, a bit error is declared (BERT.SRL:BEL = 1), and the bit error and bit counts are incremented
(BERT.RBECR
and BERT.RBCR, respectively). If the two bits do match, only the bit count is incremented. The bit
count and bit error count are not incremented when an OOS condition exists. The setting of the BEL status bit can
cause an interrupt if enabled by BERT.SRIE:BEIE.
8.5.3 Transmit Pattern Generation
The pattern generator generates the outgoing test pattern. The transmit pattern generator is a 32-bit shift register
that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit
n
y
1 is the feedback. For a PRBS pattern (generating polynomial x
+ x
+ 1), the feedback is an XOR of bit n and bit
y. For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually programmable (1
to 32 with y < n) in the BERT.PCR:PLF and PTF fields. The output of the receive pattern generator is the feedback.
If QRSS is enabled (BERT.PCR:QRSS = 1), the feedback is forced to be an XOR of bits 17 and 20, and the output
is forced to one if the next 14 bits are all zeros. For PRBS and QRSS patterns, the feedback is forced to one if bits
1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value
n
before pattern generation starts. The seed/pattern value is programmable (0 - 2
- 1) in the
BERT.SPR
registers.
The generated pattern can be inverted by setting BERT.CR:TPIC.
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