DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 70

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

9.5 LIU Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 11, 10: Jitter Attenuator Depth (JAD[1:0]). These bits select the jitter attenuator buffer depth. See Section
8.4.
Bit 9, 8: Jitter Attenuator Select (JAS[1:0]). These bits select the location of the jitter attenuator. See Section 8.4.
Bit 5: Transmit LIU LBO (TLBO). This bit is used to enable the transmit LBO circuit which causes the transmit
signal to be preattenuated to mimic the attenuation of approximately approximates about 225 feet of cable. This is
used to reduce near-end crosstalk when the cable lengths are short. This signal is only valid in DS3 and STS-1
modes. See Section 8.2.6.
Bit 4: Transmit Output Enable (TOE). This bit enables the transmitter outputs (TXP and TXN). The transmitter
continues to operate internally when the transmitter is tri-stated. Only the line driver and driver monitor are
disabled. See Section 8.2.7. Note: This bit is ORed with the associated TOE input pin.
Bit 3: Transmit Termination Resistor Enable (TTRE). This bit indicates when the transmitter internal termination
is enabled. See Section 8.2.8.
ADDRESS
OFFSET
2Ch
2Ah
2Eh
20h
22h
24h
26h
28h
00 = 16 bits
01 = 32 bits
10 = 64 bits
11 = 128 bits
00 = Disabled
01 = Receive Path
10 = Transmit Path
11 = Transmit Path
0 = Disabled
1 = Enabled
0 = TXP and TXN are high impedance
1 = TXP and TXN are driven
0 = Disabled, the transmitter is terminated externally
1 = Enabled, the transmitter is terminated internally
15
—
—
0
7
0
LIU.TWSCR1
LIU.TWSCR2
REGISTER
LIU.RGLR
LIU.SRIE
LIU.CR1
LIU.CR2
LIU.SRL
LIU.SR
14
—
—
0
6
0
LIU.CR1
LIU Control Register 1
n * 80h + 20h
TLBO
Control Register 1
Control Register 2
Transmit Waveshaping Control Register 1
Transmit Waveshaping Control Register 2
Status Register
Status Register Latched
Status Register Interrupt Enable
Receive Gain Level Register
13
—
0
5
0
REGISTER DESCRIPTION
TOE
12
—
70 of 130
0
4
0
TTRE
11
0
0
3
JAD[1:0]
10
0
2
0
DS32506/DS32508/DS32512
TRESADJ[2:0]
9
0
1
0
JAS[1:0]
8
0
0
0