DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 49

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

9. REGISTER MAPS AND DESCRIPTIONS
9.1 Overview
When a microprocessor interface is enabled
accessible. The overall memory map is shown in
of 000 to 7FFh. On the DS32508, writes in the address space for LIUs 9 through 12 are ignored, and reads from
these addresses return 00h. On the DS32506, address line A[10] is not present, and writes into the address space
for LIU 7 are ignored, and reads from these addresses return 00h. The address LSB
upper and lower bytes of a register in 8-bit mode, and to swap the upper and lower bytes in 16-bit mode.
In each register, bit 15 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are
reserved and must be written with 0 and ignored when read. Writing other values to these registers may put the
device in a factory test mode resulting in undefined operation. Bits labeled “0” or “1” must be written with that value
for proper operation. Register fields with underlined names are read-only fields; writes to these fields have no
effect. All other fields are read-write. Register fields are described in detail in the register descriptions in Sections
9.3
9.1.1 Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bit are set when the associated event occurs and remain set until cleared. Once
cleared, a latched status bit is not set again until the associated event recurs (goes away and comes back). A
latched-on-change bit is a latched status bit that is set when the event occurs and when it goes away. A latched
status bit can be cleared using either a clear-on-read or clear-on-write method (see Section 8.8.5). For clear-on-
read, all latched status bits in a latched status register are cleared when the register is read. In 16-bit mode, all 16
latched status bits are cleared. In 8-bit mode, only the eight bits read are cleared. For clear-on-write, a latched bit in
a latched status register is cleared when a logic 1 is written to that bit. For example, writing FFFFh to a 16-bit
latched status register clears all latched status bits in the register, whereas writing 0001h only clears bit 0 of the
register. When set, some latched status bits can cause an interrupt request if enabled to do so by corresponding
interrupt enable bits.
9.1.2
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—“ are reserved and must be written with 0. Configuration
registers and bits can be written to and read from during a data path reset, however, all changes to these bits are
ignored during the data path reset. As a result, all bits requiring a zero-to-one transition to initiate an action must
have the transition occur after the data path reset has been removed. See Section
resets and data path resets.
9.1.3
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the performance monitoring update signal (PMU). During a counter register update, the performance
monitoring status signal (PMS) is deasserted. A counter register update consists of loading the counter register
with the current count, resetting the counter, resetting the zero count status indication, and then asserting PMS. No
events are missed during an update. See Section
updates.
to 9.8.
Configuration Fields
Counters
(IFSEL[2:0]
Table
8.7.4
49 of 130
9-1. The DS32512 register map covers the address range
for more information about performance monitor register
≠ 000), the registers described in this section are
8.11
DS32506/DS32508/DS32512
A[0]
for more information about
is used to address the