DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 5

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

DS32506/DS32508/DS32512
LIST OF TABLES
Table 1-1. Applicable Telecommunications Standards ............................................................................................... 6
Table 7-1. Short Pin Descriptions .............................................................................................................................. 14
Table 7-2. Analog Line Interface Pin Descriptions .................................................................................................... 17
Table 7-3. Digital Framer Interface Pin Descriptions................................................................................................. 17
Table 7-4. Global Pin Descriptions ............................................................................................................................ 18
Table 7-5. Hardware Interface Pin Descriptions........................................................................................................ 19
Table 7-6. Parallel Interface Pin Descriptions ........................................................................................................... 21
Table 7-7. SPI Serial Interface Pin Descriptions ....................................................................................................... 22
Table 7-8. CLAD Pin Descriptions ............................................................................................................................. 22
Table 7-9. JTAG Pin Descriptions ............................................................................................................................. 23
Table 7-10. Power-Supply Pin Descriptions .............................................................................................................. 23
Table 7-11. Manufacturing Test Pin Descriptions...................................................................................................... 23
Table 8-1. Jitter Generation ....................................................................................................................................... 26
Table 8-2. DS3 Waveform Equations ........................................................................................................................ 27
Table 8-3. DS3 Waveform Test Parameters and Limits ............................................................................................ 27
Table 8-4. STS-1 Waveform Equations ..................................................................................................................... 28
Table 8-5. STS-1 Waveform Test Parameters and Limits......................................................................................... 28
Table 8-6. E3 Waveform Test Parameters and Limits............................................................................................... 29
Table 8-7. Transformer Characteristics ..................................................................................................................... 30
Table 8-8. Recommended Transformers................................................................................................................... 30
Table 8-9. Pseudorandom Pattern Generation.......................................................................................................... 37
Table 8-10. Repetitive Pattern Generation ................................................................................................................ 37
Table 8-11. CLAD Clock Source Settings ................................................................................................................. 41
Table 8-12. CLAD Clock Pin Output Settings............................................................................................................ 41
Table 8-13. Global One-Second Reference Source.................................................................................................. 41
Table 8-14. GPIO Pin Global Signal Assignments .................................................................................................... 42
Table 8-15. GPIO Pin Control.................................................................................................................................... 42
Table 8-16. Reset and Power-Down Sources ........................................................................................................... 48
Table 9-1. Overall Register Map................................................................................................................................ 50
Table 9-2. Port Registers........................................................................................................................................... 50
Table 9-3. Global Register Map................................................................................................................................. 51
Table 9-4. Port Common Register Map..................................................................................................................... 62
Table 10-1. JTAG ID Code ........................................................................................................................................ 91
Table 11-1. Recommended DC Operating Conditions .............................................................................................. 92
Table 11-2. DC Characteristics.................................................................................................................................. 93
Table 11-3. Framer Interface Timing ......................................................................................................................... 94
Table 11-4. Receiver Input Characteristics—DS3 and STS-1 Modes....................................................................... 96
Table 11-5. Receiver Input Characteristics—E3 Mode ............................................................................................. 96
Table 11-6. Transmitter Output Characteristics—DS3 and STS-1 Modes................................................................ 97
Table 11-7. Transmitter Output Characteristics—E3 Mode....................................................................................... 97
Table 11-8. Parallel CPU Interface Timing ................................................................................................................ 98
Table 11-9. SPI Interface Timing ............................................................................................................................. 103
Table 11-10. JTAG Interface Timing........................................................................................................................ 105
Table 12-1. Pin Assignments Sorted by Signal Name for DS32506/DS32508/DS32512 ....................................... 106
Table 14-1. Thermal Properties, Natural Convection .............................................................................................. 128
Table 14-2. Theta-JA (θ
) vs. Airflow...................................................................................................................... 128
JA
5 of 130