MAX9966BGCCQ+TD Maxim Integrated, MAX9966BGCCQ+TD Datasheet - Page 19

• Manufacturer Part Number: MAX9966BGCCQ+TD
• Description: Buffers & Line Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX9966BGCCQ+TD

• Rohs: yes

A pair of voltage clamps (high and low) can be config-
ured to limit the voltage at DUT_, and to suppress
reflections when the channel is configured as a high-
impedance receiver. The clamps behave as diodes
connected to the outputs of high-current buffers.
Internal circuitry compensates for the diode drop at
1mA clamp current. Set the clamp voltages using exter-
nal connections CPHV_ and CPLV_. The clamps are
enabled only when the driver is in the high-impedance
mode
clamp voltages to approximately the minimum and
maximum expected DUT_ voltage range and must be
empirically determined. The optimal clamp voltages are
application specific. If clamping is not desired, set the
clamp voltages at least 0.7V outside the expected
DUT_ voltage range; overvoltage protection remains
active without loading DUT_.
The MAX9965/MAX9966 have two independent high-
speed comparators for each channel. Each comparator
has one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (Figure 1).
Comparator outputs are a logical result of the input con-
ditions, as indicated in
The MAX9965/MAX9966s’ comparators feature BJT
inputs for improved comparator dispersion in contrast
to the MAX9963/MAX9964s’ JFET comparators.
Table 1. Slew Rate Logic
Table 2. Driver Logic
DATA_
CONNECTIONS
EXTERNAL
1
0
X
X
X
SC1
0
0
1
1
(Figure
RCV_
X
0
0
1
1
2). For transient suppression, set the
SC0
INTERNAL CONTROL
0
1
0
1
______________________________________________________________________________________
TMSEL
X
X
1
0
X
REGISTER
Table
DRIVER SLEW RATE (%)
3.
LLEAK
0
0
0
0
1
100
Drive to DHV_
Drive to DLV_
Drive to DTV_
(term mode)
High-impedance
mode (high-z)
Low-leakage mode
75
50
25
Comparators
DRIVER OUTPUT
Clamps
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Table 3. Comparator Logic
Figure
Figure
DUT_ > CHV_
CHV_
DUT_
CLV_
3. Open-Collector Comparator Outputs
4. Open-Emitter Comparator Outputs
DUT_
CHV_
CLV_
0
0
1
1
V
V
DUT_ > CLV_
EE
EE
8mA
8mA
0
1
0
1
106Ω
106Ω
106Ω
106Ω
OPTIONAL
4 x 48Ω
CH_
0
0
1
1
2Ω
2Ω
CH_
NCH_
V
CL_
NCL_
CCO_ _
CH_
NCH_
CL_
NCL_
CL_
0
1
0
1
V
CCO_ _
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