MAX9966BGCCQ+TD Maxim Integrated, MAX9966BGCCQ+TD Datasheet - Page 21

• Manufacturer Part Number: MAX9966BGCCQ+TD
• Description: Buffers & Line Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX9966BGCCQ+TD

• Rohs: yes

Each device supplies a single temperature output sig-
nal, TEMP, that asserts a nominal output voltage of
3.43V at a die temperature of +70°C (343K). The output
voltage increases proportionately with temperature at a
rate of 10mV/°C. The temperature sensor output imped-
ance is 15kΩ (typ).
A CMOS-compatible serial interface controls the
MAX9965/MAX9966 modes (Figure 6). Control data
flow into a bit shift register (MSB first) and are latched
when CS is taken high, as shown in the serial timing
diagram,
loaded into any or all of a group of four quad latches,
determined by bits D4 through D7, as indicated in
Figure
mode bits for each channel of the quad pin driver. The
mode bits, in conjunction with external inputs DATA_
Figure
6. Serial Interface
6 and
Figure
Serial Interface and Device Control
Table
SCLK
RST
DIN
CS
5. Data from the shift register are then
______________________________________________________________________________________
4. The quad latches contain the four
0-2
Temperature Monitor
3
7
7
TMSEL, SC0, SC1
D
ENABLE
D
ENABLE
MODE BITS CHANNEL 1
ENABLE
RST
F/F
F/F
Q
Q
0
3
LLEAK
1
1
2
0-2
SHIFT REGISTER
3
6
6
TMSEL, SC0, SC1
D
ENABLE
D
ENABLE
MODE BITS CHANNEL 2
3
RST
F/F
F/F
Quad Low-Power, 500Mbps
4
Q
Q
5
3
LLEAK
6
and RCV_, manage the features of each channel, as
shown in Tables 1 and 2. RST sets LLEAK = 1 for all
channels, forcing them into low-leakage mode. All other
bits are unaffected. At power-up, hold RST low until
V
These devices require heat removal under normal cir-
cumstances through the exposed pad, either by solder-
ing to circuit board copper (MAX9966) or by use of an
external heat sink (MAX9965). The exposed pad is
electrically at V
must be either connected to V
TRANSISTOR COUNT: 7293
PROCESS: Bipolar
ATE Driver/Comparator
1
CC
7
0-2
3
5
5
and V
TMSEL, SC0, SC1
D
ENABLE
D
ENABLE
MODE BITS CHANNEL 3
RST
F/F
F/F
EE
Q
Q
have stabilized.
3
EE
LLEAK
potential for both package types, and
1
0-2
3
4
4
TMSEL, SC0, SC1
D
ENABLE
D
ENABLE
MODE BITS CHANNEL 4
RST
F/F
F/F
Chip Information
EE
Q
Q
or isolated.
3
LLEAK
1
Heat Removal
21