MAX9966BGCCQ+TD Maxim Integrated, MAX9966BGCCQ+TD Datasheet - Page 20

• Manufacturer Part Number: MAX9966BGCCQ+TD
• Description: Buffers & Line Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX9966BGCCQ+TD

• Rohs: yes

Quad Low-Power, 500Mbps
ATE Driver/Comparator
Three configurations are available for the comparator
differential outputs to ease interfacing with a wide vari-
ety of logic families. An open-collector configuration
switches an 8mA current source between two outputs.
This configuration is available with and without internal
termination resistors connected to V
For external termination, leave V
add the required external resistors. These resistors are
typically 50Ω to the pullup voltage at the receiving end
of the output trace. Alternate configurations may be
used, provided that the Absolute Maximum Ratings are
not exceeded. For internal termination, connect V
to the desired VOH voltage. Each output provides a
nominal 400mV
An open-emitter configuration is also available
4). Connect an external collector voltage to V
add external pulldown resistors. These are typically
50Ω to V
trace. Alternate configurations may be used, provided
that the Absolute Maximum Ratings are not exceeded.
Asserting LLEAK through the serial port or with RST
places the MAX9965/MAX9966 into a very-low-leakage
state in which the DUT_ input current is less than 15nA
over the 0 to 3V range. In this mode, the driver, compara-
tors, and clamps are disabled. This mode is convenient
for making IDDQ and PMU measurements without the
need for an output disconnect relay. LLEAK is pro-
grammed independently for each channel. If DUT_ is dri-
ven with a high-speed signal while LLEAK is asserted,
leakage current momentarily increases beyond the limits
specified for normal operation. The Low-Leakage
Recovery specification in the Electrical Characteristics
table
Figure
20
______________________________________________________________________________________
indicates device behavior under this condition.
5. Serial Interface Timing
CCO_
SCLK
DIN
CS
P-P
-2V at the receiving end of the output
swing and 50Ω source termination.
Low-Leakage Mode, LLEAK
t
CH
t
CSS0
D7
CCO_
t
DS
unconnected and
D6
CCO_
t
DH
(Figure
CCO_
D5
(Figure
CCO_
and
t
CL
3).
D4
Table 4. Shift Register Functions
D3
BIT
D7
D6
D5
D4
D3
D2
D1
D0
TMSEL
LLEAK
D2
NAME
SC1
SC0
1E
2E
3E
4E
D1
Channel 1 Write Enable. Set to 1 to
update the control byte for channel 1. Set
to zero to make no change to channel 1.
Channel 2 Write Enable. Set to 1 to
update the control byte for channel 2. Set
to zero to make no change to channel 2.
Channel 3 Write Enable. Set to 1 to
update the control byte for channel 3. Set
to zero to make no change to channel 3.
Channel 4 Write Enable. Set to 1 to
update the control byte for channel 4. Set
to zero to make no change to channel 4.
Low-Leakage Select. Set to 1 to put
driver and clamps into low-leakage
mode. Set to zero for normal operation.
Driver Slew Rate Select. SC1 and SC0
set the driver slew rate. See Table 1.
Driver Termination Select. Set to 1 to
force the driver output to the DTV_
voltage (term mode) when RCV_ = 1. Set
to zero to place the driver into a high
impedance state (high-z mode) when
RCV_ = 1. See Table 2.
t
CSH1
D0
t
CSS1
FUNCTION
t
CSWH