XRT83SH314ES Exar, XRT83SH314ES Datasheet
XRT83SH314ES
Specifications of XRT83SH314ES
Related parts for XRT83SH314ES
XRT83SH314ES Summary of contents
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... T1, E1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT • Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications. • T1/E1/J1 short haul and clock rate are per port selectable through software without changing components. • Internal Impedance ...
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REV. 1.0.4 PIN OUT OF THE XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT GENERAL DESCRIPTION.............................................................................................................. 1 APPLICATIONS .......................................................................................................................................................... XRT83SH314 ................................................................................................................................. 1 IGURE LOCK IAGRAM OF THE ..................................................................................................................................................................... 1 FEATURES ................................................................................................................................ 2 RODUCT RDERING NFORMATION P O XRT83SH314..................................................................................................................................... 3 ...
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REV. 1.0.4 F 18. TAOS ( ............................................................................................................................................ 27 IGURE RANSMIT LL NES 3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27 3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... IGURE IMPLIFIED LOCK IAGRAM OF THE 3.5.2 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 48 1.5H IGURE ITTER RANSFER UNCTION F 49 10H IGURE ITTER RANSFER UNCTION F 50 ...
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REV. 1.0.4 T 55: D "ID" ABLE EVICE EGISTER 56 ABLE ICROPROCESSOR EGISTER 7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... ............................................................................................................................................. 92 ABLE BSOLUTE AXIMUM ATINGS T 58: ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PIN DESCRIPTIONS (BY FUNCTION) MICROPROCESSOR AME IN YPE CS A22 I ALE_TS C19 I WR_R/W A20 I RD_WE D18 I RDY_TA AA3 O INT B3 O µPCLK AB2 I ADDR10 ...
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REV. 1.0.4 MICROPROCESSOR AME IN YPE DATA7 AA4 I/O DATA6 AB3 DATA5 AC3 DATA4 AA5 DATA3 Y6 DATA2 AB4 DATA1 AC4 DATA0 AB5 µPTS2 AC23 I µPTS1 AB22 µPTS0 AA21 Reset B22 I CS5 B20 O CS4 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION AME IN YPE RLOS AB1 O RCLK13 AB14 O RCLK12 Y22 RCLK11 R22 RCLK10 P22 RCLK9 G22 RCLK8 F22 RCLK7 B14 RCLK6 B9 RCLK5 F2 RCLK4 G2 RCLK3 ...
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REV. 1.0.4 RECEIVER SECTION AME IN YPE RNEG13 AA14 O RNEG12 Y21 RNEG11 P21 RNEG10 N21 RNEG9 H21 RNEG8 G21 RNEG7 C14 RNEG6 C10 RNEG5 F3 RNEG4 G3 RNEG3 N3 RNEG2 P3 RNEG1 Y3 RNEG0 AA10 RTIP13 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION AME IN YPE TxON AC20 I DMO Y4 O TCLK13 Y16 I TCLK12 Y17 TCLK11 AC18 TCLK10 D16 TCLK9 C17 TCLK8 A19 TCLK7 B16 TCLK6 D7 TCLK5 A3 ...
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REV. 1.0.4 TRANSMITTER SECTION AME IN YPE TNEG13 AC17 I TNEG12 AC19 TNEG11 AA17 TNEG10 B17 TNEG9 B18 TNEG8 C18 TNEG7 C16 TNEG6 C7 TNEG5 D5 TNEG4 C5 TNEG3 C6 TNEG2 AA7 TNEG1 Y7 TNEG0 AB7 TTIP13 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT CONTROL FUNCTION AME IN YPE TEST D4 I ICT A2 I CLOCK SECTION AME IN YPE MCLKin A6 I 8kHzOUT D8 O MCLKE1out A5 O MCLKE1Nout A4 ...
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REV. 1.0.4 JTAG SECTION AME IN YPE TDI A1 I TDO D3 O POWER AND GROUND AME IN YPE TVDD13 AB13 PWR TVDD12 V21 TVDD11 T21 TVDD10 N22 TVDD9 H22 TVDD8 E21 TVDD7 B13 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND AME IN YPE DVDD_DRV C21 PWR DVDD_DRV AC2 DVDD_DRV K3 DVDD_DRV D9 DVDD_DRV AA16 DVDD_DRV U22 DVDD_PRE C3 DVDD_PRE Y5 DVDD_PRE D20 DVDD_PRE Y20 DVDD_UP AA15 AVDD_BIAS ...
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REV. 1.0.4 POWER AND GROUND AME IN YPE DGND L2 GND DGND T4 DGND C12 DGND Y12 DGND U20 DGND L23 DGND_DRV B2 GND DGND_DRV U3 DGND_DRV A16 DGND_DRV AA8 DGND_DRV L21 DGND_DRV AB23 DGND_PRE L4 DGND_PRE ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 1.0 CLOCK SYNTHESIZER In system design, fewer clocks on the network card could reduce noise and interference. Common clock references such as 8kHz are readily available to network designers. Network cards that support ...
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REV. 1.0 IGURE IMPLIFIED LOCK IAGRAM OF THE Input Clock Clock Synthesizer 8kHzOUT MCLKT1out MCLKE1out MCLKE1Nout MCLKT1Nout 1.1 ALL T1/E1 Mode To reduce system noise and power consumption, the XRT83SH314 offers an ALL T1/E1 mode. ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.1 Line Termination (RTIP/RRING) 2.1.1 CASE 1: Internal Termination The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through RTIP and RRING. The physical interface ...
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REV. 1.0.4 2.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes Along with the internal termination, a high precision external fixed resistor can be used to optimize the return loss. This external resistor can be used ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that’s in ...
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REV. 1.0 ABLE P ARAMETER RCLK Duty Cycle Receive Data Setup Time Receive Data Hold Time RCLK to Data Delay RCLK Rise Time (10% to 90%) with 25pF Loading RCLK Fall Time (90% to 10%) with 25pF ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2.2 Interference Margin The interference margin for the XRT83SH314 will be added when the first revision of silicon arrives. The test configuration for measuring the interference margin is shown ...
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REV. 1.0 IGURE NTERRUPT ENERATION (Indicates Which Channel(s) Experienced a Change in (Indicates Which Alarm Experienced a Change) (Indicates the Alarm Condition Active/Inactive The interrupt pin is an open-drain output that requires a 10kΩ ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2.3.1 RLOS (Receiver Loss of Signal mode, RLOS is declared if an incoming signal has no transitions over a period of 175 +/-75 contiguous pulse intervals. However, the XRT83SH314 LIU has ...
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REV. 1.0.4 2.2.3.4 FLSD (FIFO Limit Status Detection) The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a pre- determined range (over-flow or under-flow indication). The FLSD is set to ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.5 RPOS/RNEG/RCLK The digital output data can be programmed to either single rail or dual rail formats. diagram of a repeating "0011" pattern in single-rail mode. pattern in dual rail mode. F 12. ...
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REV. 1.0.4 3.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83SH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 17 IGURE RANSMIT ATA AMPLED ON TCLK TPOS or TNEG ABLE P ARAMETER TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise ...
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REV. 1.0.4 C ASE Input B8ZS AMI Output Input B8ZS AMI Output 3.3 Jitter Attenuator The XRT83SH314 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.5.1 ATAOS (Automatic Transmit All Ones) If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted for each channel that experiences an RLOS condition. If ...
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REV. 1.0.4 3.6.1 T1 Short Haul Line Build Out (LBO) The short haul transmitter output pulses are generated using a 7-Bit internal DAC (6-Bit plus the MSB sign bit). The line build out can be set to interface to five ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.6.3 Setting Registers to select an Aribtrary Pulse For T1: Address:0x0D hex For E1: Address: 0xF4 hex, bit D0 To program the transmit output pulse, once the arbitrary pulse has been selected, write ...
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REV. 1.0 IGURE YPICAL ONNECTION XRT83SH314 LIU Transmitter Output Internal Impedance 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT IAGRAM SING NTERNAL ERMINATION T 1:2 TIP C=0.68uF T RING One Bill of Materials 31 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.0 T1/E1 APPLICATIONS This applications section describes common T1/E1 system considerations along with references to application notes available for reference where applicable. 4.1 Loopback Diagnostics The XRT83SH314 supports several loopback modes for diagnostic ...
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REV. 1.0.4 4.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The receive input data at ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.2 84-Channel T1/E1 Multiplexer/Mapper Applications The XRT83SH314 has the capability of providing the necessary chip selects for multiple 14-channel LIU devices. The LIU is responsible for selecting itself additional LIU ...
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... System designers can achieve this by implementing common redundancy schemes with the XRT83SH314 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.3.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the ...
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REV. 1.0.4 4.3.5 Transmit Interface with N+1 Redundancy For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.3.6 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The receivers on the backup card should be programmed for "High" impedance ...
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REV. 1.0.4 4.4 Power Failure Protection For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83SH314 was ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.7 Analog Board Continuity Check This test verifies the per-channel continuity from the Line Side of TIP and RING for both the transmitters and receivers, through the transformers on the assembly and LIU. ...
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REV. 1.0 the voltaged measured ATP_TTIP/TRING pins is 1Vpp±20%, your assembly is correct The Transmitter Line Side uses a 2:1 transformer. OTE 4. If the measured signal is absent, there is either an open or short ...
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... DS-1 LIU and still maintain signal integrity. The two pieces of equipment most commonly used in the EXAR laboratory are the W&G ANT-20 and the OMNI BER from Agilent. The network analyzer runs a sweep of frequencies ranging from 10Hz to 80kHz. Each frequency step (component) becomes a data point at which the amplitude (UI, Unit Interval) is increased until bit errors are detected within the bit error tolerance ...
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REV. 1.0.4 F 36. DS IGURE ITTER OLERANCE 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT MTJ 43 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 37. DS IGURE ITTER RANSFER DISABLE URVE ARIABLE MPLITUDE 44 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT ARIABLE MPLITUDE Z 45 XRT83SH314 32 BITS ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 39 IGURE ITTER RANSFER UNCTION - BITS 46 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT - BITS 47 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 41 IGURE ITTER RANSFER UNCTION 4.8.1.2 E1 Jitter Tolerance - BITS 48 REV. 1.0.4 ...
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... E1 LIU and still maintain signal integrity. The two pieces of equipment most commonly used in the EXAR laboratory are the W&G ANT-20 and the OMNI BER from Agilent. The network analyzer runs a sweep of frequencies ranging from 10Hz to 100kHz. Each frequency step (component) becomes a data point at which the amplitude (UI, Unit Interval) is increased until bit errors are detected within the bit error tolerance ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 44 IGURE EVISION ITTER OLERANCE DB CABLE DB FLAT LOSS 50 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT - JA D ISABLED 51 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 46 IGURE ITTER RANSFER UNCTION - E1 TX 10H 32 Z BITS 52 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT - E1 TX 10H 64 Z BITS 53 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 48 IGURE ITTER RANSFER UNCTION - BITS 54 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT - E1 RX 10H 32 Z BITS 55 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 50 IGURE ITTER RANSFER UNCTION - E1 RX 10H 64 Z BITS 56 REV. 1.0.4 ...
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REV. 1.0 IGURE ITTER RANSFER UNCTION 4.8.2 Intrinsic Jitter 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT - BITS 57 XRT83SH314 ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT The intrinsic jitter is only specified on the transmit path of the LIU. Therefore best to use a Jitter Generator that can source TTL logic. This way, the transmit path can ...
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REV. 1.0 IGURE NTRINSIC ITTER 4.8.3 Jitter Transfer Curve Like the intrinsic jitter, the jitter transfer curve is only specified on the transmit path of the LIU. Therefore by applying a TTL signal ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.0 MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT83SH314S supports an Intel asynchronous interface, Motorola 68K asynchronous, and a Motorola Power PC ...
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REV. 1.0.4 5.1 The Microprocessor Interface Block Signals The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These interface signals are described below ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 17: M ABLE OTOROLA XRT83SH314S M OTOROLA T YPE AME QUIVALENT IN ALE_TS TS I WR_R/W R/W I RD_WE Pin OE I µ PCLK ...
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REV. 1.0.4 5.2 Intel Mode Programmed I/O Access (Asynchronous) If the LIU is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel type Read and Write operations are described below. Intel ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 57. I µ IGURE NTEL NTERFACE IMING N T ’HIGH’ OT IED t 5 READ OPERATION ALE t 0 ADDR [14:0] Valid Address CS DATA[7: ...
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REV. 1.0.4 F 58. I µ IGURE NTEL NTERFACE IGNALS HI GH READ OPERATION ALE = ADDR[10:0] Valid Address CS DATA[7: RDY T 19: I ABLE NTEL S P YMBOL ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.3 MPC86X Mode Programmed I/O Access (Synchronous) If the LIU is interfaced to a MPC86X type µP, it should be configured to operate in the MPC86X mode. MPC86X Read and Write operations are ...
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REV. 1.0.4 F 59. M MPC86X µP I IGURE OTOROLA TIONS READ OPERATION uPCLK Valid Address ADDR[10:0] CS DATA[7: R 20: M ABLE OTOROLA S P YMBOL ARAMETER t Valid Address to ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 60. M 68K µP I IGURE OTOROLA NTERFACE READ OPERATION _TS ALE t 0 Valid Address ADDR[10: DATA[7: _WE RD _R _DTACK RDY T ...
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REV. 1.0.4 6.0 REGISTER DESCRIPTIONS 6.1 Register Lists T 22: M ABLE R EGISTER DDRESS EX N UMBER 0x00 - 0x0F Channel 0 Control Registers 0x10 - 0x1F Channel 1 Control ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 23: M ABLE R ADDR YPE 5 0x05 RO Reserved DMO 6 0x06 RUR Reserved DMOIS 7 0x07 RO Reserved Reserved 8 0x08 R/W Reserved 1SEG6 9 0x09 ...
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REV. 1.0.4 6.2 Detail Bit Descriptions T 25: M ABLE AME D7 QRSS/PRBS QRSS/PRBS Select Bits This bit is used to select between QRSS and PRBS QRSS 1 = PRBS D6 PRBS_RX/TX PRBS Receive/Transmit Select: ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 25: M ABLE AME D5 RxON Receiver ON/OFF Upon power up, the receiver is powered OFF. RxON is used to turn the receiver ON or OFF if the hardware ...
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REV. 1.0.4 T 27: M ABLE AME D7 RxTSEL Receive Termination Select Upon power up, the receiver is in "High" impedance. RxTSEL is used to switch between the internal termination and "High" imped- ance "High" ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 28: M ABLE AME D7 INVQRSS QRSS inversion INVQRSS is used to invert the transmit QRSS pattern set by the TxTEST[2:0] bits. By default, INVQRSS is disabled and the ...
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REV. 1.0.4 T 29: M ABLE AME D4 RxRES1 Receive External Fixed Resistor D3 RxRES0 RxRES[1:0] are used to select the value for a high precision external resistor to improve return loss None 01 = ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 30: M ABLE AME D2 AISIE Alarm Indication Signal Interrupt Enable 0 = Masks the AIS function 1 = Enables Interrupt Generation D1 RLOSIE Receiver Loss of Signal Interrupt ...
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REV. 1.0 The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the OTE interrupt pin. T 31: M ABLE AME D4 LCV/OF ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 32: M ABLE AME D7 Reserved This Bit is Reserved D6 DMOIS Digital Monitor Output Status change 1 = Change in status occurred D5 FLSIS FIFO ...
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REV. 1.0.4 T 34: M ABLE AME D7 Reserved This Register Bit is Not Used D6 1SEG6 Arbitrary Pulse Generation D5 1SEG5 The transmit output pulse is divided into 8 individual segments. This register is used to ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 38: M ABLE AME D7 Reserved This Register Bit is Not Used D[6:0] 5SEG[6:0] Segment Number Five, Same Description as Register 0x08h T 39: M ABLE ...
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REV. 1.0.4 T 42: M ABLE AME D7 SR/DR Single Rail/Dual Rail Mode This bit sets the LIU to receive and transmit digital data in a single rail or a dual rail format Dual Rail ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 43: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 ...
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REV. 1.0.4 T 45: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 Reserved This Register Bit is ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 47: M ABLE AME D7 LCV/OFLW Line Code Violation / Counter Overflow Monitor Select This bit is used to select the monitoring activity between the LCV and the counter ...
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REV. 1.0.4 T 48: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 allRST LCV Counter Reset for ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 49: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used D4 ...
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REV. 1.0.4 6.2.1 Clock Select Register The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 51: M ABLE AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 ALLT1/E1 T1/E1 Control This bit is used to ...
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REV. 1.0.4 T 52: M ABLE AME D7 GCHIS7 Global Channel Interrupt Status for Channel interrupt activity from channel Interrupt was generated from channel 7 D6 GCHIS6 Global Channel Interrupt ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT AME D3 GCHIS11 Global Channel Interrupt Status for Channel interrupt activity from channel Interrupt was generated from channel 11 D2 GCHIS10 Global Channel ...
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REV. 1.0 AME D7 Device "ID" The device "ID" of the XRT83SH314S short haul LIU is 0xFEh. Along with the revision "ID", the device "ID" is used to enable soft- D6 ware to identify the silicon ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 7.0 ELECTRICAL CHARACTERISTICS Storage Temperature Operating Temperature Supply Voltage Vin T 58 ABLE VDD=3.3V ±5 ARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage IOH=2.0mA ...
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REV. 1.0 ABLE VDD=3.3V ±5 ARAMETER Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul with cable loss) Input Impedance ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 62 ABLE VDD=3.3V ±5 ARAMETER Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul ...
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REV. 1.0 ABLE VDD=3.3V ±5 ARAMETER AMI Output Pulse Amplitude 75 Ω 120 Ω Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return Loss ...
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XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT ORDERING INFORMATION P N RODUCT UMBER XRT83SH314IB PACKAGE DIMENSIONS (DIE DOWN) D SEATING PLANE A1 SYMBOL ACKAGE 304 LEAD PBGA 304 Ball Plastic Ball Grid ...
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... Added Intel Async timing diagram. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...