MC10XS3535DHFKR2 Freescale Semiconductor, MC10XS3535DHFKR2 Datasheet - Page 24

• Manufacturer Part Number: MC10XS3535DHFKR2
• Description: Power Switch ICs - Power Distribution PENTA Output ESWITCH
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3535DHFKR2

• Rohs: yes
• Number Of Outputs: 5
• On Resistance (max): 55 mOhms
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C
• Output Current: 250 mA

SERIAL INPUT (SI)
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 to D0. SI has a passive pull-down, R
SERIAL OUTPUT (SO)
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK.
24
MC10XS3535
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
The SI pin is a serial interface command data input pin.
The SO data pin is a tri-stateable output from the shift
CSB
SCLK
CS
SO
SI
NOTES:
D15
1.
2.
3.
OD15
RSTB is in a logic H state during the above operation.
DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC
OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC
Notes
D14
OD14
D13
1. D15 : D0 relate to the most recent ordered entry of data into the device.
2. OD15 : OD0 relate to the first 16 bits of ordered fault and status data out of the device.
OD13
D12
OD12
Figure 8. Single 16-Bit Word SPI Communication
D11
OD11
DOWN
CS
D10
.
OD10
D9
OD9
D8
OD8
D7
OD7
CHIP SELECT (CS)
device. When this pin is in a logic [0] state, the device is
capable of transferring information to, and receiving
information from, the master device. The 10XS3535 device
latches in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers
status information from the power output to the Shift register
on the falling edge of CS. The SO output driver is enabled
when CS is logic [0]. CS should transition from a logic [1] to a
logic [0] state only when SCLK is a logic [0]. CS has a
passive pull-up, R
The CS pin enables communication with the master
D6
OD6
D5
OD5
D4
OD4
UP
.
device.
Analog Integrated Circuit Device Data
D3
OD3
device.
D2
OD2
Freescale Semiconductor
D1
OD1
D0
OD0