MC10XS3535DHFKR2 Freescale Semiconductor, MC10XS3535DHFKR2 Datasheet - Page 38

• Manufacturer Part Number: MC10XS3535DHFKR2
• Description: Power Switch ICs - Power Distribution PENTA Output ESWITCH
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3535DHFKR2

• Rohs: yes
• Number Of Outputs: 5
• On Resistance (max): 55 mOhms
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C
• Output Current: 250 mA

EXTERNAL PIN STATUS
and IGN pins via the SPI in real time and in Normal mode.
FAILURE HANDLING STRATEGY
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
REVERSE POLARITY PROTECTION ON VBAT
output transistors are turned ON (Rsd) to prevent thermal
overloads and no protections are available.
destroy the 10XS3535 in cases of reverse polarity.
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Without loads on OUT1:5 terminal, an external
clamp between V
exceeding maximum rating. The maximum external clamp
voltage shall be between the reverse battery condition and 
-20 V.
without load on OUT outputs.
LOSS OF SUPPLY LINES
line. The detection of the supply line failure is provided inside
the device itself.
LOSS OF VBAT
V
immediately. No current path from VBAT to VCC. The
external MOSFET (OUT6) can be controlled in Normal Mode
by the SPI if VCC remains and is above
reported to the UVF bit (OD13). To delatch the fault, the
under-voltage condition should be removed and:
behavior depends on V
38
MC10XS3535
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
BAT
The 10XS3535 provides the status of the FLASHER, FOG,
A highly sophisticated failure handling strategy enables
• Reverse Polarity
• Loss of Supply Lines
• Fatal Mistreatment of Logic I/O Pins
In case of a permanently reverse polarity operation, the
An external diode on VCC is necessary in order to not to
In case of negative transients on the V
Therefore, the device is protected against latch-up with or
The 10XS3535 is protected against the loss of any supply
During an under-voltage of V
• To turn-on the output, the corresponding D7 bit must be
• If the device was in Fail mode, the fault will be delatched
In case of V
• all latched faults are reset if VCC < V
< V
rewritten to logic [1] in Normal mode. Application of the
OCHI window depends on toggling or not toggling the
D7 bit.
by the Autorestart feature periodically.
BATUV
BAT
), the outputs [1-5] are switched off
BAT
< V
and GND is mandatory to avoid
BATPOR1
CC
:
(Power OFF mode), the
BAT
(V
BATPOR1
V
BAT
CCUV
CCUV
line (per
. The fault is
<
,
LOSS OF V
10XS3535 is switched automatically into Fail mode (no
deglich time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when V
goes above
VBAT < V
LOSS OF V
not within specification: (V
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
LOSS OF GROUND (GND)
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1kohm typical). The state of the external
smart power switch controlled by FETOUT is not guaranteed,
and the state of external smart MOS is defined with an
external termination resistor.
FATAL MISTREATMENT OF LOGIC I / O PINS
by signal plausibility check according to
than 10ms typical, the 10XS3535 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is provided
and the bit D7 defines the outputs state. In case of SPI failure,
the 10XS3535 is switched into Fail mode (see
• all latched faults are maintained under V
During loss of V
If the external V
During loss of ground, the 10XS3535 cannot operate the
The digital I / Os are protected against fatal mistreatment
In case the LIMP input is set to logic [1] for a delay longer
SPI (MOSI, SCLK, CS
conditions. In case V
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting (if V
range for at least 35 sec), and daisy-chain features are
provided for RST is set to logic [1]. The SPI pull-up and
pull-down current resistors are available. This fault
condition can be diagnosed with UVF fault in OD13
reporting bit. The previous device configuration is
maintained. No current is conducted from V
(PWM) CLOCK
Input / Output
BATPOR2
Table 16. Logic I / O Plausibility Check
V
LIMP
CC
CC
CCUV
(DIGITAL LOGIC SUPPLY LINE)
AND VBAT
BAT
. The device will transit in OFF mode if
.
CC
BAT
(V
and V
Analog Integrated Circuit Device Data
was previously in the nominal voltage
CC
)
CC
BAT
< V
CC
and V
is disconnected, OUT[1:5]
CCUV
supplies are disconnected (or
WD, D10 bit internal toggle
Signal Check Strategy
Freescale Semiconductor
BAT
) and with wake=1, the
Debounce for 10ms
Frequency range
(bandpass filter)
) < V
Table
BATPOR1
CC
16.
Figure
CC
in nominal
), all SPI
to V
18)
CC
BAT
.