MC10XS3535DHFKR2 Freescale Semiconductor, MC10XS3535DHFKR2 Datasheet - Page 30

• Manufacturer Part Number: MC10XS3535DHFKR2
• Description: Power Switch ICs - Power Distribution PENTA Output ESWITCH
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3535DHFKR2

• Rohs: yes
• Number Of Outputs: 5
• On Resistance (max): 55 mOhms
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C
• Output Current: 250 mA

ADDRESS 00000 — INITIALIZATION
statuses, choose one of the six outputs current recopy, load
the H7 bulbs profile for OUT2 only, enable the FOG pin and
synchronize the switching phases between different devices.
The register bits D1 and D0 determine the content of the 16
bits of the next SO data. (Refer to the section entitled
Output Communication (Device Status Return Data)
ADDRESS 00001 — CONFIGURATION OL
load detection for LEDs in Normal Mode (OLLEDn in
page 29) and to active the LED Control.
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
for output 1.
30
MC10XS3535
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
D6 (PWM sync) = 0, No synchronization
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D5 (Xenon) = 0, Xenon
D5 (Xenon) = 1, H7 Bulb
D7 (FOGen) = 0, FOG pin does not control the output 4
D7 (FOGen) = 1, FOG input controls the output 4
D15
The Initialization register is used to read the various
The Configuration OL register is used to enable the open
When bit D0 is set to logic [1], the open load detection
When bit D5 is set to logic [1], the LED Control is activated
0
D14
0
SI Address
D13
0
D12
0
D11
0
D10
WD
Table 9. Initialization Register
D9
0
Table
Serial
8,
D8
0
FOGen
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current
sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog
feedback
D7
beginning on page 31.)
initialization.
long as the WD bit (D10) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally. If an internal
watchdog timeout occurs before the WD bit is toggled, the
device will revert to Fail mode. All registers are cleared. To
exit the Fail mode, send valid SPI communication with
WD bit = 1.
ADDRESS 00010 — CONFIGURATION PRESCALER
AND SR
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
slew-rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
The watchdog timeout is specified by
Two configuration registers are available at this address.
The Configuration Prescaler register is used to enable the
The SR Prescaler register is used to increase the output
PWM
sync
D6
SI Data
Xenon
D5
MUX2
Analog Integrated Circuit Device Data
D4
Table 9
MUX1
D3
describes the register of
Freescale Semiconductor
MUX0
t
D2
WDTO
parameter. As
SOA1
D1
SOA0
D0