MCIMX6S6AVM08AB Freescale Semiconductor, MCIMX6S6AVM08AB Datasheet - Page 14

• Manufacturer Part Number: MCIMX6S6AVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6S6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Modules List
14
Block Mnemonic
IOMUXC
MLB150
IPUv3H
MMDC
KPP
LDB
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Image Processing Unit,
LVDS Display Bridge
Multi-Mode DDR
IOMUX Control
Block Name
Key Pad Port
Controller
MediaLB
ver.3H
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
System Control
Connectivity /
Subsystem
Connectivity
Connectivity
Connectivity
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Multimedia
Multimedia
This module enables flexible IO multiplexing. Each IO
pad has default and several alternate functions. The
alternate functions are software configurable.
IPUv3H enables connectivity to displays and video
sources, relevant processing and synchronization and
control capabilities, allowing autonomous operation.
The IPUv3H supports concurrent output to two display
ports and concurrent input from two camera ports,
through the following interfaces:
The processing includes:
KPP Supports 8x8 external key pad matrix. KPP
features are:
LVDS Display Bridge is used to connect the IPU (Image
Processing Unit) to External LVDS Display Interface.
LDB supports two channels; each channel has following
signals:
Each signal pair contains LVDS special differential pad
(PadP, PadM).
The MLB interface module provides a link to a MOST
data network, using the standardized MediaLB protocol
(up to 6144 fs).
The module is backward compatible to MLB-50.
DDR Controller has the following features:
• Parallel Interfaces for both display and camera
• Single/dual channel LVDS display interface
• HDMI transmitter
• MIPI/DSI transmitter
• MIPI/CSI-2 receiver
• Image conversions: resizing, rotation, inversion, and
• A high-quality de-interlacing filter
• Video/graphics combining
• Image enhancement: color adjustment and gamut
• Support for display backlight reduction
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
• One clock pair
• Four data pairs
• Supports 16/32-bit DDR3-800 (LV) or LPDDR2-800
• Supports 16/32/64-bit DDR3-800 (LV) or
• Supports 2x32 LPDDR2-800 in i.MX 6DualLite
• Supports up to 4 GByte DDR memory space
color space conversion
mapping, gamma correction, and contrast
enhancement
in i.MX 6Solo
LPDDR2-800 in i.MX 6DualLite
Brief Description
Freescale Semiconductor
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