MCIMX6S6AVM08AB Freescale Semiconductor, MCIMX6S6AVM08AB Datasheet - Page 90
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MCIMX6S6AVM08AB
Manufacturer Part Number
MCIMX6S6AVM08AB
Description
Processors - Application Specialized i.MX6 Solo rev 1.1
Manufacturer
Freescale Semiconductor
Type
Automotive and Infotainment Processorsr
Datasheet
1.MCIMX6S6AVM08AB.pdf
(174 pages)
Specifications of MCIMX6S6AVM08AB
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Instruction / Data Cache Memory
32 KB
Data Ram Size
128 KB
Data Rom Size
96 KB
Operating Supply Voltage
1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
BGA 2240
Interface Type
I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
Memory Type
DDR3
Minimum Operating Temperature
- 40 C
Number Of Timers
2
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX6S6AVM08AB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX6S6AVM08AB
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MCIMX6S6AVM08ABR
Manufacturer:
FSC
Quantity:
200
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Electrical Characteristics
4.11.5.1.4
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 50
shown in the figure.
4.11.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the CRS_DV in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET_RX_ER.
90
M10
M11
M12
M13
M14
M15
ID
ENET_MDIO (output)
ENET_MDC (output)
ENET_MDIO (input)
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
ENET_MDC pulse width low
shows MII asynchronous input timings.
MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Figure 50. MII Serial Management Channel Timing Diagram
Table 63. MII Serial Management Channel Timing
Characteristic
M12
M13
Table 63
M14
describes the timing parameters (M10–M15)
Min.
40%
40%
M10
18
—
0
0
M11
M15
Max.
60%
60%
—
—
—
5
Freescale Semiconductor
ENET_MDC period
ENET_MDC period
Unit
ns
ns
ns
ns
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