MCIMX6S7CVM08AB Freescale Semiconductor, MCIMX6S7CVM08AB Datasheet - Page 11

• Manufacturer Part Number: MCIMX6S7CVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S7CVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Freescale Semiconductor
Mnemonic
OCOTP_C
OCRAM_L
IOMUXC
OCRAM
OSC 32
PWM-1
PWM-2
PWM-3
PWM-4
MMDC
LCDIF
Block
PMU
KPP
TRL
kHz
2
On-Chip Memory
On-Chip Memory
Power-Managem
Multi-Mode DDR
Controller for L2
IOMUX Control
OTP Controller
LCD Interface
Key Pad Port
Block Name
OSC 32 kHz
ent functions
Pulse Width
Modulation
Controller
controller
Cache
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 2. i.MX 6SoloLite Modules List (continued)
Connectivity
Connectivity
Connectivity
Subsystem
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Multimedia
Data Path
Data Path
Data Path
Clocking
Security
System
Control
This module enables flexible IO multiplexing. Each IO pad has default and
several alternate functions. The alternate functions are software configurable.
KPP Supports 8 x 8 external key pad matrix. KPP features are:
The LCDIF provides display data for external LCD panels from simple
text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF
supports all of these different interfaces by providing fully programmable
functionality and sharing register space, FIFOs, and ALU resources at the
same time. The LCDIF supports RGB (DOTCLK) modes as well as system
mode including both VSYNC and WSYNC modes.
DDR Controller has the following features:
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control information
stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals, requiring permanent
non-volatility.
The On-Chip Memory controller (OCRAM) module is designed as an interface
between system’s AXI bus and internal (on-chip) SRAM memory module.
In i.MX 6SoloLite processor, the OCRAM is used for controlling the 128 KB
multimedia RAM through a 64-bit AXI bus.
The On-Chip Memory controller for L2 cache (OCRAM_L2) module is
designed as an interface between system’s AXI bus and internal (on-chip) L2
cache memory module during boot mode.
Generates 32.768 kHz clock from external crystal.
Integrated power management unit. Used to provide power to various SoC
domains.
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images and it can also generate
tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound.
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
• Support 16/32-bit DDR3-800 or LPDDR2-800
• Supports up to 2 GByte DDR memory space
Brief Description
Modules List
11