MCIMX6S7CVM08AB Freescale Semiconductor, MCIMX6S7CVM08AB Datasheet - Page 5

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MCIMX6S7CVM08AB

Manufacturer Part Number
MCIMX6S7CVM08AB
Description
Processors - Application Specialized i.MX6 Solo rev 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX6S7CVM08AB

Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Data Ram Size
128 KB
Maximum Operating Temperature
+ 105
Mounting Style
SMD/SMT
Package / Case
MAPBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX6S7CVM08AB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.2
The i.MX 6SoloLite processor is based on ARM Cortex-A9 MPCore™ Platform, which has the
following features:
The ARM Cortex-A9 MPCore complex includes:
The memory system consists of the following components:
Each i.MX 6SoloLite processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
Freescale Semiconductor
ARM Cortex-A9 MPCore CPU Processor (with TrustZone)
The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
General Interrupt Controller (GIC) with 128 interrupt support
Global Timer
Snoop Control Unit (SCU)
256 KB unified I/D L2 cache
Two Master AXI (64-bit) bus interfaces output of L2 cache
Frequency of the core (including Neon and L1 cache) as per
21
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
Level 1 Cache—32 KB Instruction, 32 KB Data cache per core
Level 2 Cache—Unified instruction and data (256 KByte)
On-Chip Memory:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
External memory interfaces:
— 16-bit, and 32-bit DDR3-800, and LPDDR2-800 channels
— 16/32-bit NOR Flash.
— 16/32-bit PSRAM, Cellular RAM (32 bits or less)
Displays—Total three interfaces are available.
— LCD, 24bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz)
Features
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 9, "Operating Ranges," on page
Introduction
5

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