MCIMX6S7CVM08AB Freescale Semiconductor, MCIMX6S7CVM08AB Datasheet - Page 74

• Manufacturer Part Number: MCIMX6S7CVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S7CVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
3
4
Electrical Characteristics
4.10.7
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
74
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
C
IC10
IC11
IC12
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
b
ID
= total capacitance of one bus line in pF.
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
Pulse Width Modulator (PWM) Timing Parameters
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Parameter
Table 57. I
b
)
2
C Module Timing Parameters
Min
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
—
—
—
Standard Mode
1
3.45
1000
Max
300
400
—
—
—
—
—
—
—
—
2
Freescale Semiconductor
20 + 0.1C
20 + 0.1C
100
Fast Mode
Min
2.5
0.6
0.6
0.6
1.3
0.6
1.3
0
—
1
3
b
b
4
4
Max
0.9
300
300
400
—
—
—
—
—
—
—
—
2
Unit
pF
µ
µ
µ
µ
µ
µ
µ
ns
µ
ns
ns
s
s
s
s
s
s
s
s