P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 144

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

Hardware Design Considerations
3.3
3.3.1
Each of the PLLs described in
(AV
directly from the V
the SV
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in
Figure
from one PLL to the other is reduced.
144
DD_PLAT
DD
54, one for each of the AV
Default (0_0000)
IO_VSEL[0:4]
source through a low frequency filter scheme.
Power Supply Design
, AV
Signals
PLL Power Supply Filtering
DD_CCn
DD_PL
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
, AV
source through a low frequency filter scheme. AV
DD_DDR
Section 3.1, “System Clocking,”
DD
pins. By providing independent filters to each PLL the opportunity to cause noise injection
, and AV
All Others
(Binary)
0_0000
0_0001
0_0011
0_0100
0_0110
0_0111
0_1001
0_1010
0_1100
0_1101
0_1111
1_0000
1_0010
1_0011
1_0101
1_0110
1_1000
1_1001
1_1011
1_1100
1_1101
1_1110
1_1111
Value
Table 110. I/O Voltage Selection
DD_SRDSn
). AV
DD_PLAT
is provided with power through independent power supply pins
BVDD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
, AV
DD_CCn
DD_SRDSn
VDD Voltage Selection
and AV
voltages must be derived directly from
Reserved
CVDD
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
DD_DDR
voltages must be derived
Freescale Semiconductor
LVDD
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V