P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 68

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

Electrical Characteristics
This table provides the system clock (SYSCLK) AC timing specifications.
2.6.2
Spread spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in
jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns;
the chip is compatible with spread spectrum sources if the recommendations listed in
68
For recommended operating conditions, see
For recommended operating conditions, see
SYSCLK frequency
SYSCLK cycle time
SYSCLK duty cycle
SYSCLK slew rate
SYSCLK peak period jitter
SYSCLK jitter phase noise at – 56dBc
AC Input Swing Limits at 3.3 V OV
Note:
Frequency modulation
Frequency spread
Note:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their
2. Measured at the rising edge and/or the falling edge at OV
3. Slew rate as measured from ±0.3 ΔV
4. Phase noise is calculated as FFT of TIE jitter.
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
respective maximum or minimum operating frequencies.
maximum specifications given in
Parameter/Condition
Spread Spectrum Sources
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which
the processor is operated at its maximum rated core/platform/DDR frequency should avoid
violating the stated limits by using down-spreading only.
Parameter
Table 15
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 15. Spread Spectrum Clock Source Recommendations
considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
DD
Table 14. SYSCLK AC Timing Specifications
Table
Table
Table
AC
t
KHK
14.
Symbol
f
t
at center of peak to peak voltage at clock input.
SYSCLK
SYSCLK
3.
3.
ΔV
/ t
—
—
—
SYSCLK
AC
CAUTION
DD
Min
—
—
Min
100
1.9
40
—
—
/2.
6
1
Typ
Max
1.0
—
—
—
—
—
—
—
60
Table 15
are observed.
Max
166
150
500
10
60
—
4
Unit
kHz
%
Freescale Semiconductor
MHz
Unit
V/ns
KHz
ns
ps
%
V
Note
1,
—
2
Note
1,
1,
—
—
2
3
4
2
2