P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 155

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

3.6.3
This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when
it is partly unused.
3.6.3.1
If the high-speed SerDes interface is not used at all, the unused pin must be terminated as described in this section.
The following pins must be left unconnected:
The following pins must be connected to SGND:
The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2 and SRDS_LPD_B3, all bits must be set to power down all
the lanes in each bank.
The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting
RCW[SRDS_EN] = 0 powers down the PLLs of all three banks.
Additionally, software may configure SRDSBnRSTCTL[SDRD]
PLLs to save power.
Note that both SV
3.6.3.2
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
Leave these pins unconnected:
Connect these unused pins to SGND:
In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must
be set to power down the lane.
3.6.4
This section details the hardware connections required for the USB controllers.
Freescale Semiconductor
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SD_TX[17:0]
SD_TX[17:0]
SD_IMP_CAL_RX
SD_IMP_CAL_TX
SD_RX[17:0]
SD_RX[17:0]
SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3
SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3
SD_TX[n]
SD_TX[n]
SD_RX[n]
SD_RX[n]
SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)
SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)
SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused)
Guidelines for High-Speed Interface Termination
USB Controller Connections
SerDes Interface Entirely Unused
SerDes Interface Partly Unused
DD
and XV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD
must remain powered.
=
1 for the unused banks to power down the SerDes bank
Hardware Design Considerations
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