P5020NXN1TNB Freescale Semiconductor, P5020NXN1TNB Datasheet - Page 102

• Manufacturer Part Number: P5020NXN1TNB
• Description: Processors - Application Specialized P5020 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXN1TNB

• Rohs: yes

Electrical Characteristics
This figure provides the AC test load for the I
This figure shows the AC timing diagram for the I
102
For recommended operating conditions, see
Noise margin at the LOW level for each connected
device (including hysteresis)
Noise margin at the HIGH level for each connected
device (including hysteresis)
Capacitive load for each bus line
Note:
1. The symbols used for timing specifications herein follow the pattern t
2. The requirements for I
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the V
4. The maximum t
SDA
SCL
for inputs and t
(I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
the high (H) state or setup time. Also, t
condition (S) went invalid (X) relative to the t
symbolizes I
to the t
the I2C Frequency Divider Ratio for SCL.”
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, application note AN2919 referred to in note 2 above is recommended.
S
I2C
clock reference (K) going to the high (H) state or setup time.
2
C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
t
t
(first two letters of functional block)(reference)(state)(signal)(state)
I2CL
I2SXKL
I2OVKL
Parameter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
2
must be met only if the device does not stretch the LOW period (t
C frequency calculation must be followed. Refer to Freescale application note AN2919, “Determining
Output
Table 58. I
t
I2DXKL,
Table
Figure 34. I
I2SXKL
t
2
I2DVKH
3.
t
2
I2OVKL
C AC Timing Specifications (continued)
Figure 33. I
C.
I2C
t
Z
symbolizes I
I2CH
0
2
C bus.
= 50 Ω
clock reference (K) going to the low (L) state or hold time. Also, t
2
C Bus AC Timing Diagram
t
I2SXKL
Symbol
2
C AC Test Load
2
V
V
C timing (I2) for the time that the data with respect to the START
Cb
NH
NL
Sr
1
t
I2SVKH
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
0.1 × OV
0.2 × OV
R
L
Min
= 50 Ω
—
DD
DD
t
I2PVKH
t
I2KHKL
OV
I2CL
DD
I2C
) of the SCL signal.
/2
Max
I2DVKH
400
—
—
clock reference (K) going to
P
Freescale Semiconductor
symbolizes I
IHmin
S
Unit
pF
V
V
of the SCL
t
I2PVKH
I2KHDX
2
C timing
Note
—
—
—