P5020NXN1TNB Freescale Semiconductor, P5020NXN1TNB Datasheet - Page 70

• Manufacturer Part Number: P5020NXN1TNB
• Description: Processors - Application Specialized P5020 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXN1TNB

• Rohs: yes

Electrical Characteristics
This table provides the PLL lock times.
2.8
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate
specifications.
2.9
This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note
that the required GV
interfacing to DDR3L SDRAM.
70
Input setup time for POR configs with respect to negation of PORESET
Input hold time for all POR configs with respect to negation of PORESET
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of PORESET
Note:
PLL lock times
Required ramp rate for all voltage supplies (including OV
GV
Note:
1. SYSCLK is the primary clock input for the chip.
2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device
3. PORESET must be driven asserted before the core and platform power supplies are powered up. Refer to
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change
2. Over full recommended operating temperature range (see
DD
releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in
Section 4.4.1 “Power-On Reset Sequence,” of the reference manual for your chip.
“Power Up
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
/BV
DD
Power-on Ramp Rate
DDR3 and DDR3L SDRAM Controller
/SV
Sequencing.”
Parameter
DD
/XV
DD
DD
(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
/LV
Table 17. RESET Initialization Timing Specifications (continued)
DD
Parameter
all V
DD
Parameter
supplies, MVREF and all AV
Table 19. Power Supply Ramp Rate
Table 18. PLL Lock Times
Min
—
DD
/CV
Table
DD
/
DD
3).
supplies.)
Max
100
Min
—
4
2
Min
DD
—
Max
—
—
5
Unit
(typ) voltage is 1.35 V when
μs
36000
Max
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
Unit
1
Unit
V/s
Section 2.2,
Note
—
Note
1
1
1
Note
1,
2