P5020NXN1TNB Freescale Semiconductor, P5020NXN1TNB Datasheet - Page 131

• Manufacturer Part Number: P5020NXN1TNB
• Description: Processors - Application Specialized P5020 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXN1TNB

• Rohs: yes

2.20.8.4
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.
For recommended operating conditions, see
This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.
The AC timing specifications do not include RefClk jitter.
2.20.9
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in
C
output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference
circuit of the SerDes transmitter and receiver is shown in
2.20.9.0.1
When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock
is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII
configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see
Freescale Semiconductor
For recommended operating conditions, see
Unit Interval
Total jitter data-data 5 UI
Total jitter, data-data 250 UI
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
Note:
Unit Interval
Total jitter f
Total jitter f
Total jitter f
Deterministic jitter, f
Deterministic jitter, f
Deterministic jitter, f
Note:
1. Measured at receiver.
1. Measured at receiver.
TX
is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω
C3dB
C3dB
C3dB
Parameter
SGMII Interface
Parameter
AC Differential Receiver Input Characteristics
= f
= f
= f
SGMII Clocking Requirements for SD_REF_CLKn and SD_REF_CLKn
BAUD
BAUD
BAUD
C3dB
C3dB
C3dB
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
÷ 10
÷ 500
÷ 1667
= f
= f
= f
BAUD
BAUD
BAUD
Table 91. Gen 1i/1.5G Receiver (Rx) AC Specifications
Table 92. Gen 2i/3G Receiver (Rx) AC Specifications
÷ 10
÷ 500
÷ 1667
Table
Table
U
U
U
U
U
U
SATA_TXDJ250UI
SATA_TXTJ250UI
U
U
U
U
SATA_TXDJ5UI
SATA_TXTJ5UI
SATA_TXDJfB/1667
SATA_TXTJfB/1667
SATA_TXDJfB/500
3.
SATA_TXTJfB/500
3.
Symbol
SATA_TXTJfB/10
SATA_TXDJfB/10
Symbol
T
UI
T
Section 2.20.2, “SerDes Reference Clocks.”
UI
Figure
666.4333
333.2167
43.
Min
—
—
—
—
Min
—
—
—
—
—
—
333.3333
666.6667
Typical
Typical
—
—
—
—
—
—
—
—
—
—
335.1167
670.2333
Max
0.46
0.60
0.65
0.35
0.42
0.35
Max
0.43
0.60
0.25
0.35
Electrical Characteristics
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Unit
Figure
Unit
ps
ps
48, where
Note
Note
—
—
1
1
1
1
1
1
1
1
1
1
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