P5020NXN1TNB Freescale Semiconductor, P5020NXN1TNB Datasheet - Page 148

• Manufacturer Part Number: P5020NXN1TNB
• Description: Processors - Application Specialized P5020 Ext Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXN1TNB

• Rohs: yes

Hardware Design Considerations
3.6.1
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in
Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most
have asynchronous behavior and spurious assertion gives unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be
asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST
during the power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also used for
accessing the common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
PORESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in
target can drive PORESET as well. The COP interface has a standard header, shown in
system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector
typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering
schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom.
Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal
placement recommended in
3.6.1.1
If the JTAG interface and COP header is not used, Freescale recommends the following connections:
148
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For P5010, the voltage rail VDD_CB must be connected to GND.
TRST should be tied to PORESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal
(PORESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in
isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future
debug situations.
No pull-up/pull-down is required for TDI, TMS, or TDO.
Legacy JTAG Configuration Signals
Termination of Unused Signals
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Figure 59
Figure 58
allows the COP port to independently assert PORESET or TRST, while ensuring that the
is common to all known emulators.
Figure
Figure
59. If this is not possible, the
58, for connection to the target
Freescale Semiconductor
Figure
59.