P5010NSN1TNB Freescale Semiconductor, P5010NSN1TNB Datasheet - Page 111

• Manufacturer Part Number: P5010NSN1TNB
• Description: Processors - Application Specialized P5010 Std Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSN1TNB

• Rohs: yes

2.20.4
This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.
2.20.4.1
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
2.20.4.2
SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations
based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3.
For more information on these specifications, see
2.20.4.3
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.3.1
This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Freescale Semiconductor
For recommended operating conditions, see
Differential peak-to-peak
output voltage
De-emphasized differential
output voltage (ratio)
DC differential Tx
impedance
Transmitter DC impedance Z
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
Parameter
Table 63. PCI Express 2.0 (2.5 GT/s) Differential Transmitter (Tx) Output DC Specifications
PCI Express
Clocking Dependencies
PCI Express Clocking Requirements for SD_REF_CLKn and
SD_REF_CLKn
PCI Express DC Physical Layer Specifications
PCI Express DC Physical Layer Transmitter Specifications
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
V
V
Z
TX-DIFFp-p
TX-DE-RATIO
TX-DIFF-DC
TX-DC
Symbol
Table
3.
Min
800
3.0
80
40
(XV
Section 2.20.2, “SerDes Reference Clocks.”
Typical
DD
100
3.5
50
—
= 1.5 V or 1.8 V)
1200
Max
120
4.0
60
Unit
mV
dB
Ω
Ω
V
Ratio of the V
following bits after a transition divided by the
V
Note 1.
Tx DC differential mode low Impedance
Required Tx D+ as well as D– DC Impedance
during all states
TX-DIFFp-p
TX-DIFFp-p
of the first bit after a transition. See
= 2 × |V
TX-DIFFp-p
TX-D+
Note
Electrical Characteristics
of the second and
– V
TX-D-
| See Note 1.
111