P5010NSN1TNB Freescale Semiconductor, P5010NSN1TNB Datasheet - Page 5

• Manufacturer Part Number: P5010NSN1TNB
• Description: Processors - Application Specialized P5010 Std Tmp NoEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSN1TNB

• Rohs: yes

AD
AG
AH
AM
AN
AR
Freescale Semiconductor
AA
AB
AC
AE
AF
AK
AP
AJ
AL
AT
M
W
A
B
C
D
E
G
H
K
N
P
R
U
V
Y
F
L
T
J
MAPAR_
D2_MA
D2_MA
D2_MA
D2_MA
D2_MA
MDQS
MECC
MDQS
MDQS
MRAS
MODT
MODT
MDQS
MDQS
RSRV
RSRV
MDM
RSRV
RSRV
MDQ
MDQ
MDQ
MDQ
MBA
MCK
MCK
OUT
MBA
MCS
MCS
MDQ
MDQ
[AK1]
[AL1]
MDQ
MDQ
MDQ
D2_
[16]
D2_
D2_
[22]
D2_
[19]
[G1]
D2_
[31]
D2_
D2_
D2_
D2_
[12]
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
[38]
D2_
[35]
D2_
[52]
D2_
[48]
D2_
D2_
D2_
[50]
[F1]
[2]
[0]
[8]
[8]
[2]
[9]
[6]
[3]
[1]
[2]
[3]
[1]
[0]
[2]
[1]
[1]
[4]
[6]
[6]
1
1
MAPAR_
D2_MA
D2_MA
D2_MA
D2_MA
Signal Groups
GV DD
MDQS
GV DD
GV DD
MECC
GV DD
GV DD
GV DD
GV DD
GV DD
MODT
GV DD
MDQS
GV DD
GV DD
GV DD
MDQ
MDQ
RSRV
RSRV
MDM
MWE
MDQ
RSRV
RSRV
[AL2]
MDQ
MDM
MDQ
ERR
MCK
MCK
MCS
[AK2]
D2_
[21]
D2_
D2_
[23]
[12]
[F2]
[G2]
[21]
D2_
D2_
[25]
[15]
D2_
[31]
[36]
D2_
D2_
[43]
[10]
D2_
[45]
D2_
D2_
[49]
D2_
[33]
D2_
[57]
[63]
D2_
[53]
D2_
[42]
D2_
[51]
[1]
[2]
[5]
[8]
[8]
[4]
[2]
[3]
[0]
[3]
2
[4]
[6]
2
D2_MA
D2_MA
D2_MA
MDQS
MDQS
MECC
MECC
MCAS
MODT
MDQ
MDQ
GND
MDQ
MDQ
GND
MDM
MDQ
GND
GND
GND
MCK
GND
MDQ
GND
MDQ
GND
MDM
GND
MDQ
MDQ
MDQ
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
GND
D2_
MCK
D2_
GND
D2_
MBA
D2_
MCS
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
OV DD
LV DD
GV DD
CV DD
BV DD
[20]
[17]
[18]
[29]
[30]
[41]
[14]
[11]
[42]
[50]
[51]
[58]
[37]
[62]
[34]
[66]
[67]
[49]
[54]
[55]
[1]
[3]
[3]
[8]
[1]
[6]
[5]
[1]
[0]
[0]
[2]
[3]
[4]
[5]
[5]
3
3
D2_MA
D2_MA
D2_MA
D2_MA
MECC
MECC
MDQS
MDQS
GV DD
GV DD
GV DD
MCKE
GV DD
MCKE
GV DD
MDIC
GV DD
GV DD
GV DD
GV DD
GV DD
MDQ
MDQ
MDM
MDQ
MDQ
MDQ
MCK
MCK
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D1_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
[10]
[11]
[28]
[24]
[16]
[26]
[24]
[28]
[34]
[51]
[13]
[48]
[36]
[32]
[56]
[39]
[45]
[61]
[42]
[68]
[60]
[61]
[2]
[7]
[4]
[7]
[3]
[2]
[7]
[2]
[1]
[0]
[0]
[0]
[4]
[5]
4
4
I/O Supply Voltage
I/O Supply Voltage
DDR DRAM I/O Supply
SPI Voltage Supply
Local Bus I/O Supply
MDQS
MDQS
MECC
MDQS
MECC
MECC
MCKE
MDQS
MDQS
MCKE
MDIC
GND
MDQ
MDQ
GND
MDQ
GND
GND
GND
GND
MCK
MCK
GND
MDQ
GND
MDQ
GND
MDQ
GND
MDQ
MDQ
GND
MDQ
MDQ
GND
MDQ
D2_
D2_
[14]
D2_
[15]
D2_
[25]
D2_
D1_
D1_
[40]
D2_
D2_
[43]
D2_
D2_
[49]
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D2_
D2_
D2_
D2_
D2_
[52]
[36]
[57]
[38]
[61]
[40]
[65]
[44]
[41]
[68]
[43]
[56]
[73]
[57]
[1]
[2]
[4]
[3]
[9]
[1]
[8]
[2]
[3]
[0]
[1]
[1]
[0]
[1]
[4]
[5]
5
5
D1_MA
D1_MA
D1_MA
D1_MA
MDQS
GV DD
GV DD
MDQS
GV DD
MDQS
GV DD
GV DD
GV DD
GV DD
GV DD
MDQS
GV DD
GV DD
MDQS
MDQS
MDM
MDIC
MDIC
MDM
MDQ
MDQ
MDQ
MCK
MCK
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
D2_
D2_
D2_
D1_
[22]
[13]
D2_
D2_
[27]
[22]
D1_
[15]
[27]
[12]
[32]
D1_
D1_
D1_
D2_
[41]
D1_
[37]
D1_
[33]
[46]
D1_
[39]
D1_
[34]
[54]
D1_
D1_
[46]
[60]
D2_
[40]
D2_
[46]
[67]
D2_
D2_
D2_
6
[1]
[1]
[6]
[9]
[3]
[8]
[9]
[0]
[1]
[1]
[0]
[1]
[5]
[7]
[7]
[7]
6
MAPAR_
D1_MA
D1_MA
D1_MA
D1_MA
D1_MA
MECC
MECC
GV DD
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDM
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
GND
GND
SEE DETAIL A
GND
GND
GND
GND
OUT
GND
GND
SEE DETAIL C
GND
GND
GND
D2_
D2_
[13]
D2_
[12]
D1_
[23]
D1_
[24]
[10]
D1_
[30]
D1_
[39]
D1_
[14]
[44]
[11]
[48]
[38]
[53]
D1_
[10]
[56]
D1_
[32]
D1_
[60]
D1_
[35]
D1_
[45]
[64]
D1_
[47]
D1_
[53]
[69]
D2_
[47]
D1_
[54]
[74]
D2_
[62]
D2_
[63]
[8]
[5]
[5]
[6]
[8]
[2]
[4]
7
7
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
MAPAR_
MDQS
MECC
D1_MA
D1_MA
D1_MA
GV DD
GV DD
MDQS
GV DD
GV DD
GV DD
GV DD
GV DD
GV DD
MODT
GV DD
GV DD
GV DD
GV DD
MDQ
MDQ
MDQ
MDM
MWE
MDQ
MDM
MDQ
MDQ
MDQ
MDQ
MDQ
D2_
D1_
D1_
D1_
D1_
D1_
D1_
MBA
ERR
MCK
MCK
MBA
[16]
[11]
[29]
D1_
[20]
[26]
D1_
[30]
[37]
D1_
D1_
[44]
D1_
D1_
[53]
D1_
[13]
[50]
D1_
[44]
D1_
[58]
D1_
[52]
D1_
[49]
[64]
D1_
[55]
D2_
[58]
[15]
D2_
[59]
[3]
[2]
[2]
[3]
[4]
[8]
[2]
[7]
[5]
[2]
[3]
[0]
[2]
[5]
8
8
Figure 3. P5020—1295 BGA Ball Map Diagram (Top View)
D1_MA
D1_MA
D1_MA
MDQS
MDQS
MECC
MECC
MCKE
MCKE
MDQS
MDQ
MDQ
GND
MDQ
GND
MDQ
GND
GND
GND
MCK
MCK
GND
MCS
MCS
GND
MCS
MCS
GND
MDQ
MDQ
GND
MDQ
GND
MDQ
MDQ
MDQ
D2_
D2_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
[18]
[11]
[31]
[38]
[45]
[47]
[55]
[59]
[63]
[41]
[42]
[70]
[48]
[75]
[60]
[61]
[56]
[7]
[2]
[6]
[2]
[3]
[0]
[7]
[3]
[2]
[6]
[3]
[2]
[3]
[0]
[2]
[0]
[1]
[3]
[6]
9
9
D1_MA
MDQS
GV DD
GV DD
GV DD
MECC
MECC
GV DD
MCKE
MCKE
GV DD
GV DD
MRAS
GV DD
MCAS
MODT
GV DD
MODT
MODT
GV DD
GV DD
GV DD
MDQS
GV DD
MDQ
MDQ
MDQ
MDQ
MDQ
MDQ
GND
MBA
MDQ
MDQ
MDQ
MDM
D2_
D2_
D1_
[21]
D1_
[19]
D1_
[28]
[17]
D1_
[26]
D1_
[27]
[23]
D1_
D1_
[29]
D1_
D1_
[33]
[54]
[40]
D1_
D1_
[52]
D1_
D1_
[47]
D1_
D1_
[55]
D1_
[43]
[39]
[62]
D1_
D1_
[50]
[65]
D1_
[57]
D1_
10
10
[0]
[6]
[8]
[2]
[3]
[0]
[1]
[4]
[1]
[0]
[3]
[1]
[6]
[7]
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
SENSE-
MDQS
[AG11]
[AH11]
[AP11]
MDQS
MDQ
MDM
MDQ
[K11]
RSRV
RSRV
MDM
GND
GND
MDM
[J11]
GND
[113]
GND
[113]
GND
[115]
GND
[116]
GND
[117]
GND
[118]
GND
[119]
GND
GND
MDQ
GND
11
D2_
D1_
[20]
D1_
[12]
D1_
[25]
D1_
GND
[24]
[26]
[10]
[11]
[27]
[12]
[71]
IRQ
D1_
[76]
D1_
[51]
[80]
D1_
11
[0]
[7]
[2]
[37]
NC
NC
[8]
[9]
NC
SV DD
XV DD
VDD_
VDD_
VDD_
[3]
[1]
[9]
[6]
[7]
CA
CB
PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
SENSE-
GND_PL
[AG12]
[AH12]
[AM12]
GV DD
GV DD
GV DD
RSRV
RSRV
OV DD
GV DD
MDQS
MDQ
MDM
MDQ
[H12]
MDQ
MDQ
MDQ
MDQ
[K12]
GND
[230]
GND
[126]
GND
[125]
GND
[124]
GND
[123]
GND
[122]
GND
[121]
GND
[120]
12
D2_
D2_
D1_
[17]
D1_
[10]
[14]
D1_
[11]
[25]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
IRQ
IRQ
[11]
[66]
D1_
[63]
D1_
[62]
D1_
12
[1]
NC
NC
[5]
[2]
NC
[7]
[0]
[5]
[1]
SerDes Core Power Supply
SerDes Transcvr Pad Supply
Platform Supply Voltage
Core Group A Supply Voltage
Core Group B Supply Voltage
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
[AN13]
MDQ
MDQ
MDQ
GND
MDQ
MDQ
GND
[H13]
[J13]
[K13]
GND
[127]
[N13]
GND
[128]
GND
[129]
GND
[130]
GND
[131]
GND
[132]
GND
[133]
GND
GND
IIC3_
GND
GND
MDQ
MDQ
D2_
D2_
D2_
D1_
D1_
IRQ
IRQ
SCL
IRQ
D1_
D1_
13
[13]
[14]
[15]
[35]
NC
NC
NC
[63]
[88]
[31]
[59]
[87]
[82]
[20]
[85]
[72]
[77]
NC
[81]
[59]
[58]
13
[4]
[5]
[0]
[8]
[5]
[7]
VDD_PL
VDD_CA
VDD_PL
VDD_PL
VDD_PL
VDD_CB
VDD_PL
VDD_PL
MDQS
MDQS
[AP14]
GV DD
GV DD
GV DD
GV DD
OV DD
[AT14]
MDQ
MDQ
MDM
[J14]
[K14]
GND
[141]
GND
[N14]
GND
[139]
GND
[138]
GND
[137]
GND
[136]
GND
[135]
GND
[134]
IIC4_
IRQ_
OUT
IIC2_
IIC3_
IIC1_
D1_
D1_
D1_
D1_
D1_
SCL
IRQ
SDA
SDA
SDA
14
[10]
[19]
NC
NC
[89]
[92]
[61]
[97]
[93]
[70]
[10]
NC
[59]
NC
14
[3]
[3]
[2]
[1]
[1]
[1]
[5]
[5]
[2]
VDD_CA
VDD_CA
VDD_CB
VDD_CB
VDD_CB
VDD_PL
VDD_PL
VDD_PL
VDD_CB
SENSE-
MDVAL
OV DD
[H15]
IIC1_
IIC4_
IIC2_
MDQ
MDQ
GND
MDQ
MDQ
GND
MDQ
LWE
GND
[142]
GND
[P15]
GND
[144]
GND
[145]
GND
[146]
GND
[147]
GND
[148]
GND
[149]
SCL
GND
SDA
SCL
GND
TDO
D1_
D1_
[14]
D1_
D1_
[13]
[36]
D1_
[30]
[64]
[10]
[15]
[77]
[21]
IRQ
[78]
[82]
15
NC
15
[6]
[7]
[8]
[9]
LA
[3]
[1]
[8]
[9]
[3]
[9]
VDD_CA
VDD_CA
VDD_CA
VDD_CB
VDD_CB
VDD_PL
VDD_PL
GND_CB
RESET_
VDD_CA
VDD_PL
SENSE-
SENSE-
MDQS
MDQS
GV DD
GV DD
OV DD
OV DD
MDM
[E16]
MDQ
LDP
LWE
GND
GND
[156]
GND
[155]
GND
[154]
GND
[150]
GND
[152]
GND
[151]
GND
[153]
EVT
EVT
EVT
GND
REQ
16
D1_
D1_
D1_
D1_
[12]
[18]
[98]
[11]
[12]
[22]
[15]
[94]
[58]
IRQ
IRQ
[11]
[92]
16
NC
[7]
[1]
[0]
[3]
[4]
[4]
[2]
[0]
[0]
[0]
[9]
[3]
[2]
[9]
GND_CA
VDD_PL
VDD_CA
VDD_CA
VDD_PL
VDD_CB
VDD_CB
VDD_CB
VDD_PL
PORESET
HRESET
SENSE-
POVDD
SCAN_
MODE
MDQ
MDQ
MDQ
MDQ
GND
[P17]
GND
[163]
GND
[164]
GND
[165]
GND
[166]
GND
D1_
GND
[231]
LDP
LAD
GND
[157]
GND
GND
[159]
GND
[222]
EVT
EVT
17
D1_
D1_
D1_
[25]
[31]
[15]
[65]
[16]
[13]
[90]
[12]
[10]
[11]
[23]
IRQ
IRQ
[83]
TDI
17
[1]
LA
[2]
[6]
[4]
[0]
[1]
[0]
[5]
[4]
VDD_CA
VDD_CA
VDD_CA
VDD_PL
VDD_CB
VDD_CB
VDD_PL
VDD_PL
MSRCID
GV DD
AVDD_
BV DD
OV DD
VSEL
VSEL
VSEL
OV DD
VSEL
GND
GND
[D18]
GND
GND
GND
[161]
GND
[162]
GND
[167]
GND
[169]
GND
[168]
GND
[170]
GND
GND
LAD
LAD
LAD
160]
CC2
18
[24]
[31]
NC
[28]
[29]
[31]
[13]
[14]
[32]
[17]
[18]
[14]
[62]
[13]
[14]
[95]
[60]
[79]
IO_
IO_
IO_
IO_
[86]
18
[4]
LA
LA
[9]
[2]
[3]
[2]
[0]
[3]
[6]
[1]
VDD_CA
VDD_CA
VDD_CB
VDD_CB
VDD_CB
MSRCID
VDD_PL
VDD_PL
VDD_PL
CKSTP_
DETECT
AVDD_
MVREF
DMA2_
DMA1_
RSRV
[AT19]
[C19]
VSEL
TMP_
TRST
DDR
LCS
GND
LAD
GND
GND
[178]
GND
[177]
GND
[176]
GND
[175]
GND
[174]
GND
[173]
GND
[172]
GND
[171]
DACK
GND
DACK
OUT
GND
SENSE-
VDD_PL
[18]
[12]
[28]
[29]
[30]
[15]
[66]
[91]
[16]
[25]
IO_
[84]
[88]
19
NC
[0]
LA
LA
LA
[6]
[4]
19
AVDD_
SRDS1
AVDD_
SRDS2
AVDD_
AVDD_
[2]
[3]
[0]
[4]
[1]
[0]
PLAT
CC
VDD_CA
VDD_CA
VDD_CA
VDD_PL
VDD_CB
VDD_CB
VDD_PL
VDD_PL
MSRCID
AVDD_
DDONE
AVDD_
BV DD
BV DD
DMA2_
OV DD
DMA2_
GND
[C20]
GND
GND
[179]
GND
[180]
GND
[181]
GND
[185]
GND
[183]
GND
[184]
GND
[182]
GPIO
DREQ
CLK_
GPIO
GPIO
PLAT
CC1
LCS
LCS
OUT
TMS
20
[16]
NC
[25]
[26]
[27]
[22]
[28]
[17]
[96]
[57]
20
[1]
[2]
[3]
LA
[8]
LA
LA
[7]
[2]
[1]
[4]
[7]
[0]
[8]
[2]
[3]
[0]
[0]
SerDes 1 PLL Supply Voltage
SerDes 2 PLL Supply Voltage
Platform PLL Supply Voltage
Core PLL Supply Voltage
Platform Voltage Sense
VDD_PL
VDD_CA
VDD_CA
VDD_PL
VDD_PL
VDD_CB
VDD_PL
VDD_PL
ASLEEP
ANODE
RSRD
TEMP_
TEMP_
DDONE
TEST_
CATH-
OV DD
DMA1_
DMA1_
GND
[190]
GND
[189]
GND
[188]
GND
[187]
GND
[186]
GPIO
GPIO
GPIO
GPIO
GND
DREQ
[A21]
ODE
LCS
GND
GND
GND
[193]
GND
[192]
GND
[191]
SEL
21
[21]
[22]
[29]
[23]
[33]
[24]
[67]
[75]
[76]
[78]
[29]
[90]
21
[3]
LA
LA
LA
LA
[8]
[3]
[6]
[7]
[4]
[5]
[6]
[0]
[0]
[0]
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
UART2_
UART1_
UART1_
UART1_
LBCTL
BV DD
BV DD
SOUT
GPIO
SOUT
OV DD
GND
GND
GND
GND
[200]
GND
[199]
GND
[198]
GND
[197]
GND
[196]
GND
[195]
GND
[194]
GND
GND
LCS
LAD
LAD
RTS
CTS
TCK
22
[21]
[17]
[19]
[11]
[20]
[10]
[19]
[80]
[83]
[84]
[30]
[85]
[86]
[79]
[56]
PD
[17]
[89]
[93]
22
[4]
[6]
LA
LA
[2]
[1]
[1]
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
UART2_
UART2_
UART2_
UART1_
SYSCLK
SHDC_
SDHC_
LALE
LCLK
OV DD
GND
GND
GND
[208]
GND
[207]
GND
[206]
GND
[205]
GND
[204]
GND
[203]
GND
[202]
GND
[201]
GND
LCS
LAD
LAD
[26]
LAD
[18]
[20]
LDP
[68]
[71]
[72]
[33]
CTS
RTS
CLK
DAT
SIN
SIN
23
[34]
[73]
[74]
[37]
PD
[13]
[10]
[94]
23
[5]
[1]
[9]
[8]
[7]
LA
[1]
[2]
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
BV DD
BV DD
BV DD
CV DD
USB1_
AGND
USB1_
AGND
USB1_
USB1_
CLKIN
OV DD
LCLK
VDD_
USB_
LWE
LWE
GND
[209]
GND
[210]
GND
[211]
GND
[212]
GND
[213]
GND
[214]
GND
[215]
GND
[216]
RTC
LCS
LAD
LAD
LDP
[38]
[39]
[40]
[41]
[42]
[43]
[44]
[55]
UID
3P3
[12]
[15]
24
[3]
PD
[14]
PD
24
[1]
[1]
[0]
[0]
[5]
[6]
[6]
[5]
[0]
[7]
SEE DETAIL D
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
[AG25]
VBUS_
USB1_
RSRV
RSRV
USB1_
USB1_
USB1_
USB1_
USB1_
AGND
USB2_
AGND
USB2_
AGND
AGND
USB1_
[A25]
LGPL
LGPL
LGPL
LGPL
VDD_
VDD_
CLMP
AGND
AGND
LAD
LAD
GND
GND
[225]
GND
[224]
GND
[223]
GND
GND
[220]
GND
[219]
GND
[218]
GND
[217]
[17]
SEE DETAIL B
[16]
[30]
[69]
[45]
[46]
[47]
[46]
[48]
[49]
[50]
[54]
25
[0]
[4]
[2]
[1]
[4]
LA
[3]
LA
1P0
3P3
25
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
[AG26]
VBUS_
VDD_1P8
BV DD
[AF26]
USB2_
USB2_
USB2_
_DECAP
USB2_
USB2_
USB1_
USB1_
[B26]
[C26]
LGPL
LGPL
VDD_
VDD_
CLMP
USB1_
USB1_
AGND
AGND
GND
LAD
LCS
LAD
LAD
LAD
GND
[112]
GND
[111]
GND
[110]
GND
[109]
GND
[108]
GND
[107]
GND
[106]
IBIAS_
UDM
UDM
[23]
[27]
1P0
3P3
REXT
26
NC
NC
[5]
[4]
[7]
[3]
[2]
[0]
[1]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
NC
NC
26
Pin Assignments and Reset States
SD_IMP_
CAL_RX
GND_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
SENSE-
SENSE-
VDD_1P8
[AF27]
[AG27]
USB2_
USB2_
USB2_
_DECAP
USB2_
USB1_
[W27]
AGND
VDD_
USB2_
IBIAS_
AGND
USB2_
AGND
USB1_
[A27]
[C27]
[D27]
[E27]
GND
[G27]
[H27]
GND
GND
GND
[221]
GND
[226]
GND
[227]
GND
[228]
GND
GND
[229]
GND
TMS
USB2_
REXT
VDD_CB
3P3
UID
27
NC
NC
NC
NC
[28]
NC
NC
[27]
[34]
[51]
[32]
[52]
NC
[35]
[87]
[36]
[97]
NC
NC
UDP
UDP
27
SENSE-
SENSE-
POVDD
[2]
[2]
RSRV
VDD
VDD_PL
_DETECT
SD_RX
SD_RX
LP_TMP
SPI_CS
SGND
XGND
SD_TX
SD_TX
XGND
[AA28]
[AB28]
[AC28]
[AF28]
[AG28]
USB2_
USB2_
USB2_
USB2_
SV DD
XV DD
XV DD
RSRD
RSRD
RSRD
RSRD
MISO
USB1_
AGND
USB2_
AGND
AGND
AGND
AGND
AGND
[R28]
[T28]
[U28]
[V28]
[Y28]
VDD_
SPI_
GND
[10]
[10]
[15]
[20]
[L28]
[M28]
[N28]
[P28]
[53]
[96]
28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
28
[1]
[9]
[0]
[0]
[0]
[0]
[1]
LP
Core Group A Voltage Sense
Core Group B Voltage Sense
Reserved
Fuse Programming Override Supply
SD_RX
SD_RX
SPI_CS
SPI_CS
SPI_CS
SD_TX
SD_TX
XGND
XGND
XGND
SD_TX
[AB29]
[AC29]
[AD29]
[AE29]
[AF29]
[AG29]
RX_ER
SGND
SV DD
XGND
XGND
XGND
XGND
XV DD
XGND
XV DD
XV DD
XGND
XV DD
XV DD
CV DD
CV DD
MOSI
EC2_
SPI_
GND
SPI_
CLK
29
[12]
[15]
[13]
[15]
[18]
[21]
[22]
[21]
[25]
[28]
[25]
[27]
[32]
[34]
[32]
[13]
NC
NC
NC
NC
NC
NC
[91]
29
[1]
[1]
[1]
[1]
[1]
[1]
[3]
[0]
[2]
[2]
1588_PULSE
1588_CLK_
SD_IMP_
SD_RX
SD_RX
CAL_TX
SGND
SD_TX
SD_TX
XGND
XGND
SD_TX
XGND
SD_TX
XGND
XGND
XGND
[AH30]
EMI2_
EMI2_
_OUT[1]
TSEC_
SV DD
XGND
XV DD
XV DD
XV DD
XV DD
XGND
XV DD
XV DD
XV DD
XV DD
XV DD
XGND
MDIO
TSEC_
MDC
OUT
GND
[101]
30
[10]
[11]
[11]
[16]
[18]
[19]
[24]
[26]
[23]
[30]
[11]
[29]
[30]
[36]
[13]
NC
PD
PD
PD
30
[1]
[2]
[2]
[2]
[2]
[1]
[2]
[3]
[5]
[6]
[8]
[2]
[3]
[4]
EC_XTRNL
_TX_STMP
EC_XTRNL
_RX_STMP
EC_XTRNL
_TX_STMP
SD_RX
SD_RX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SV DD
SGND
XGND
XV DD
XGND
XV DD
XV DD
XV DD
XGND
XGND
XV DD
XV DD
XGND
XV DD
XGND
REF_
CLK3
LV DD
LV DD
[12]
[14]
[14]
[13]
[19]
[20]
[22]
[10]
[26]
[11]
[33]
[35]
[12]
[33]
[14]
SD_
[16]
[17]
[38]
[12]
31
[3]
[3]
[3]
[3]
[7]
[8]
PD
PD
PD
31
[3]
[6]
[7]
[2]
[2]
[3]
[2]
[9]
[1]
[1]
EC_XTRNL
_RX_STMP
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SD_TX
SGND
SV DD
RSRD
RSRD
XV DD
XGND
XV DD
XGND
XV DD
XGND
XGND
XGND
XV DD
XV DD
XGND
XGND
XV DD
XGND
XV DD
EMI1_
RSRD
REF_
CLK3
MDIO
SD_
GND
[100]
GND
[105]
GND
[10]
[C32]
[D32]
[12]
[12]
[16]
[17]
[23]
[27]
[10]
[31]
[28]
[U32]
[31]
[12]
[37]
[14]
[16]
[17]
[34]
[95]
32
[2]
[8]
[7]
[8]
[2]
[5]
[7]
PD
PD
PD
32
[1]
[6]
[7]
[8]
AVDD_
SRDS1
AGND_
SRDS1
SD_TX
SD_TX
SD_TX
SD_RX
SD_TX
SD_RX
SD_RX
SD_TX
SD_RX
CLK125
SGND
XGND
XV DD
XV DD
SGND
SV DD
XV DD
SGND
SV DD
SGND
SV DD
XV DD
RSRD
SV DD
SGND
SGND
EMI1_
REF_
CLK2
[AD33]
LV DD
EC1_
LV DD
MDC
EC2_
GTX_
RXD
33
[13]
[14]
[20]
[22]
[24]
[24]
[11]
[26]
SD_
[29]
[13]
[15]
[16]
[32]
[10]
[11]
33
PD
PD
PD
[9]
[9]
[5]
[5]
[6]
[8]
[9]
[3]
[4]
[6]
[9]
[1]
[3]
[4]
[5]
1588_PULSE
SD_TX
SD_TX
SD_TX
SD_RX
SD_TX
SD_RX
SD_RX
SD_TX
SD_RX
_OUT[2]
CLK125
RX_DV
SV DD
SGND
SV DD
SV DD
SGND
XGND
SV DD
SGND
XGND
SV DD
SGND
SV DD
SGND
XGND
RSRD
SGND
SV DD
REF_
CLK2
[AD34]
TSEC_
GTX_
EC1_
EC1_
EC1_
EC1_
SD_
GND
[102]
EC1_
GND
[104]
RXD
GND
TXD
TXD
34
[11]
[13]
[17]
[17]
[17]
[20]
[22]
[29]
[24]
[11]
[27]
[28]
[13]
[15]
[16]
[99]
34
[2]
[4]
[4]
[6]
[9]
[4]
[4]
[7]
[8]
[2]
[1]
[2]
[8]
1588_ALARM
1588_CLK
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SRDS3
SD_RX
AVDD_
_OUT[2]
SV DD
SGND
SGND
SV DD
SGND
SV DD
SGND
SV DD
SGND
RSRD
SV DD
SGND
SV DD
SGND
SV DD
SGND
LV DD
TSEC_
TSEC_
LV DD
GTX_
LV DD
REF_
CLK1
REF_
CLK1
EC1_
EC1_
EC1_
SD_
SD_
[U35]
RXD
CLK
TXD
35
[14]
[15]
[16]
[18]
[19]
[21]
[23]
[10]
[25]
[26]
[27]
[12]
[30]
[14]
[15]
[17]
[31]
_IN
35
[5]
[6]
[7]
[9]
[4]
[6]
[7]
[5]
[7]
[1]
[6]
[0]
1588_ALARM
1588_TRIG
1588_TRIG
RX_CLK
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
SD_RX
AGND_
SRDS2
SRDS2
SD_RX
SD_RX
SD_RX
AGND_
SRDS3
SD_RX
SGND
SGND
SGND
SGND
AVDD_
SGND
SGND
_OUT[1]
TX_EN
SV DD
SV DD
SV DD
SV DD
SV DD
SV DD
SGND
SV DD
TSEC_
TSEC_
EC1_
EC1_
TSEC_
_IN[2]
_IN[1]
EC1_
EC1_
GND
[103]
RXD
TXD
36
[11]
[16]
[18]
[19]
[21]
[23]
[10]
[25]
[28]
[12]
[29]
[14]
[15]
[17]
[30]
36
[3]
[4]
[4]
[5]
[6]
[7]
[9]
[5]
[5]
[8]
[0]
[3]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
5