P5020NXE1TNB Freescale Semiconductor, P5020NXE1TNB Datasheet - Page 104

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P5020NXE1TNB

Manufacturer Part Number
P5020NXE1TNB
Description
Processors - Application Specialized P5020 ExtTmpEnc 1800/1333 r2.0
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of P5020NXE1TNB

Rohs
yes
Electrical Characteristics
2.19.2
This table provides the GPIO input and output AC timing specifications.
This figure provides the AC test load for the GPIO.
2.20
The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, Serial RapidIO, XAUI, Aurora and SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference
clocks. The SerDes data lane’s transmitter (Tx) and receiver (Rx) reference circuits are also shown.
2.20.1
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
104
For recommended operating conditions, see
GPIO inputs—minimum pulse width
Trust inputs—minimum pulse width
Note:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
2. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least t
external synchronous logic. GPIO inputs are required to be valid for at least t
operation. For low power trust input pin LP_TMP_DETECT, the voltage is VDD_LP and see
requirement.
High-Speed Serial Interfaces (HSSI)
GPIO AC Timing Specifications
Signal Terms Definition
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Output
Parameter
Table 61. GPIO Input AC Timing Specifications
Table
3.
Figure 35. GPIO AC Test Load
Z
0
= 50 Ω
R
L
= 50 Ω
Symbol
PIWID
t
t
PIWID
TIWID
to ensure proper operation.
OV
DD
Table 3
/2
Min
20
3
Freescale Semiconductor
TIWID
for the voltage
SYSCLK
Unit
to ensure proper
ns
Note
1
2

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