P5020NXE1TNB Freescale Semiconductor, P5020NXE1TNB Datasheet - Page 53

• Manufacturer Part Number: P5020NXE1TNB
• Description: Processors - Application Specialized P5020 ExtTmpEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXE1TNB

• Rohs: yes

Notes:
1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
2. This pin is an open drain signal.
3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
5. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BV
6. This output is actively driven during reset rather than being three-stated during reset.
7. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair
9. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding
11. Do not connect.
12. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV
13. Independent supplies derived from board V
14. Recommend a pull-up resistor of 1-kΩ be placed on this pin to OV
15. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
16. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 20-Ω (full-strength mode) or 40.2-Ω (half-strength mode)
18. These pins should be pulled up to 1.2V through a 180Ω
20. Pin has a weak internal pull-up.
21. These pins should be pulled to ground (GND).
22. Ethernet Management Interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage
23. This pin requires a 200-Ω pull-up to XV
24. This pin requires a 200-Ω pull-up to SV
25. This GPIO pin is on LV
26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined
27. See
28. For P5010, this signal must be pulled low to GND.
29. For P5010, voltage rail must be connected to GND.
30. Warning, incorrect voltage select settings can lead to irreversible device damage. See
31. SDHC_DAT[4:7] require CV
32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XV
Freescale Semiconductor
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ resistor. However, if the signal is
intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then
a pull up or active driver is needed.
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
to possible noise, and so forth.
to be used by the voltage regulators with remote sense function.
that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device.
driven.
precision 1% resistor and Dn_MDIC[1] is connected to GV
mode) precision 1% resistor. These pins are used for automatic calibration of the DDR3 and DDR3L IOs.
EM2_MDIO.
levels. LV
by the RCW.
Setting.”
Incorrect voltage select settings can lead to irreversible device damage.
Section 3.6, “Connection
DD
must be powered to use this interface.
Signal
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD
power plane, not OV
DD
Recommendations,” for additional details on this signal.
= 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.
Table 1. Pins Listed by Bus (continued)
DD
DD
.
.
DD_PL
DD
.
(Core Complex, Platform, DDR) or SV
Signal Description
± 1%
DD
through an 20-Ω (full-strength mode) or 40.2-Ω (half-strength
resistor for EM2_MDC and a 330Ω
DD
if I2C interface is used.
DD
DD
, to ensure no random chip select assertion due
.
Pin Number
DD
Package
Pin Assignments and Reset States
Section 3.2, “Supply Power Default
DD
for normal chip operation.
(SerDes).
± 1%
Type
Pin
resistor for
Supply
Power
DD
Notes
pin.
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