P5020NXE1TNB Freescale Semiconductor, P5020NXE1TNB Datasheet - Page 142

• Manufacturer Part Number: P5020NXE1TNB
• Description: Processors - Application Specialized P5020 ExtTmpEnc 1800/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NXE1TNB

• Rohs: yes

Hardware Design Considerations
3.1.7
The clock ratio between each of the three SerDes PLLs and their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field SRDS_RATIO_Bn
as shown in this table. Furthermore, each SerDes lane grouping can be run at a SerDes PLL frequency divider determined by
the binary value of the RCW field SRDS_DIV_Bn as shown in
This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios.
This table shows the PLL divider support for each pair of lanes on SerDes Bank 1.
This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2 and 3.
3.1.8
The frame managers, FM, can each be synchronous with or asynchronous to the platform, depending on configuration.
This table describes the clocking options that may be applied to each FM. The clock selection is determined by the binary value
of the RCW Clocking Configuration fields FM_CLK_SEL.
142
Note:
Note:
1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes, where the first bit controls configuration of lanes A/B (or 0/1)
1. One bit controls all 4 lanes of each bank.
2. n = 2 or 3 (SerDes bank 2 or bank 3)
SRDS_RATIO_B1
and the last bit controls configuration of lanes I/J (or 8/9).
Binary Value of
Binary Value of SRDS_DIV_B1[0:4]
All Others
001
010
011
100
101
110
SerDes PLL Ratio
Frame Manager Clock Select
Binary Value of SRDS_DIV_Bn
0b0
0b1
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 106. SerDes PLL Bank n to SD_REF_CLKn Ratios
0b0
0b1
Table 108. SerDes Banks 2 and 3 PLL Dividers
n = 1 (Bank 1)
Reserved
Reserved
Reserved
Reserved
Table 107. SerDes Bank 1 PLL Dividers
25:1
40:1
50:1
SRDS_PLL_n:SD_REF_CLKn Ratio
Table 107
n = 2 (Bank 2)
Reserved
Reserved
Reserved
SerDes Bank 1 PLL Divider
Divide by 1 off Bank 1 PLL
Divide by 2 off Bank 1 PLL
and
20:1
25:1
40:1
50:1
Table
SerDes Bank n PLL Divider
Divide by 1 off Bank n PLL
Divide by 2 off Bank n PLL
108.
Freescale Semiconductor
n = 3 (Bank 3)
Reserved
20:1
25:1
40:1
50:1
24:1
30:1