P5020NXE1TNB Freescale Semiconductor, P5020NXE1TNB Datasheet - Page 110

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P5020NXE1TNB

Manufacturer Part Number
P5020NXE1TNB
Description
Processors - Application Specialized P5020 ExtTmpEnc 1800/1333 r2.0
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of P5020NXE1TNB

Rohs
yes
Electrical Characteristics
2.20.2.4
SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock and the industry protocol specifications supports it. For better
results, a source without significant unintended modulation should be used.
SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application
usage:
Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard
requirements.
110
Section 2.20.4, “PCI Express”
Section 2.20.5, “Serial RapidIO (sRIO)”
Section 2.20.6, “XAUI”
Section 2.20.7, “Aurora”
Section 2.20.8, “Serial ATA (SATA)
Section 2.20.9, “SGMII Interface”
SerDes Transmitter and Receiver Reference Circuits
Spread Spectrum Clock
Figure 42. Single-Ended Measurement Points for Rise and Fall Time Matching
Transmitter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Figure 43. SerDes Transmitter and Receiver Reference Circuits
50 Ω
50 Ω
SD_TXn
SD_TXn
SD_RXn
SD_RXn
50 Ω
50 Ω
Receiver
Freescale Semiconductor

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