MCIMX6Q4AVT08AC Freescale Semiconductor, MCIMX6Q4AVT08AC Datasheet - Page 48

• Manufacturer Part Number: MCIMX6Q4AVT08AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.8.2
The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.
Table 36
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 W external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.8.3
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
4.8.4
Table 37
48
Differential Output Impedance
Output Driver
Impedance
Parameter
shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors.
shows MLB 6-pin I/O differential output impedance of i.MX 6Dual/6Quad processors.
Parameter
DDR I/O Output Buffer Impedance
LVDS I/O Output Buffer Impedance
MLB 6-Pin I/O Differential Output Impedance
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Symbol
Rdrv
Table 37. MLB 6-Pin I/O Differential Output Impedance
Symbol
Table 36. DDR I/O Output Buffer Impedance
Z
Drive Strength (DSE) =
O
Test Conditions
000
001
010
011
100
101
110
111
Test Conditions
—
NVCC_DRAM=1.5 V
DDR_SEL=11
(DDR3)
Hi-Z
240
120
80
60
48
40
34
Min
1.6
Typical
NVCC_DRAM=1.2 V
DDR_SEL=10
(LPDDR2)
Typ
—
Hi-Z
240
120
80
60
48
40
34
Freescale Semiconductor
Max
—
Unit

Unit
k